CHECK-NOT: zeroinitializer also matched unrelated select instructions
used for masked address computation on some targets (e.g. host CI's
4-wide target), causing false failures unrelated to the decrement fix.
Scope the negative check to the actual buggy pattern: add ..., zeroinitializer.
Co-Authored-By: Claude Sonnet 5 <noreply@anthropic.com>
lLLVMConstantValue() cast a negative double directly to an unsigned
integer type (e.g. (unsigned int)(-1.0)) when emitting the step
constant for varying unsigned decrement. This conversion is undefined
behavior in C++ for out-of-range values; on aarch64 hosts it saturates
to 0, silently turning `--` into a no-op, and for UINT64 it tripped an
Assert. Route the conversion through a signed intermediate type first,
which is well-defined for -1, then narrow to the unsigned type.
LLVM trunk (23.0) removed CpuInfo::getImpliedExtensions() method.
Access the DefaultExtensions field directly for LLVM 23+, while
maintaining backward compatibility with LLVM 22 and earlier.
Co-authored-by: aneshlya <aneshlya@users.noreply.github.com>
Build LLVM+ISPC only for fix tasks, drop the redundant issues:[opened]
trigger, and remove the unused checkout from the dedup workflow, which now
classifies non-duplicate issues by type (Bug/Enhancement).
Co-Authored-By: Claude Opus 4.8 (1M context) <noreply@anthropic.com>
Greets first-time PR authors via actions/first-interaction. Uses
pull_request_target but checks out no fork code and only posts a comment.
Co-Authored-By: Claude Opus 4.8 (1M context) <noreply@anthropic.com>
Auto-requests review from the code owner, documents additional maintainers
who are not auto-requested, and posts a thank-you comment linking to
CONTRIBUTING on new issues from non-maintainers.
Co-Authored-By: Claude Opus 4.8 (1M context) <noreply@anthropic.com>
The Xe int8 add helpers were instantiated via xe_add(i16, int8),
defining __add_varying_int8/__add_uniform_int8 over i16 while
__reduce_add_int8 calls them with i8 operands. The resulting
implicit bitcast-call is undefined behavior and produced wrong
results for reduce_add on negative int8/uint8 values. Use
xe_add(i8, int8) so the helper types match.
Co-Authored-By: Claude Opus 4.8 (1M context) <noreply@anthropic.com>
Split full test flow into basic/avx512/avx10 groups, move LLVM 20/21 to a
weekly llvm-legacy workflow, and default to the newer SDE (overriding to the
older 9.58.0 only for basic/avx512). Fix the avx10 SDE ternary so NVL targets
get the newer SDE that supports the -nvl knob.
* Fix#3782: Migrate optimization pass emission to poison
Replace UndefValue::get with PoisonValue::get in optimization passes
where intermediate vectors are created as placeholders before being
filled with loaded or computed values. Using poison instead of undef
enables LLVM to apply stronger optimizations (e.g. eliminating dead
code in select chains).
Replace all occurrences of the deprecated undef keyword with poison in ISPC's
built-in IR library files (builtins/*.ll) and M4 macro files
(builtins/util.m4, builtins/util-xe.m4, builtins/svml.m4).
Co-Authored-By: Claude Sonnet 4.6 <noreply@anthropic.com>
- Fixed _mm_shuffle_pd to use 1-bit selector fields instead of 2-bit fields
- The intrinsic now correctly interprets the immediate as two 1-bit selectors
(one for each output lane) instead of treating it like _mm_shuffle_ps
- Added LIT test covering all four shuffle masks: (0,0), (0,1), (1,0), (1,1)
- Added functional test to verify runtime correctness
- Updated copyright year to 2026
Co-authored-by: aneshlya <aneshlya@users.noreply.github.com>
LLVM trunk changed IRBuilder::CreateIntrinsic to return Value* instead
of CallInst* to allow constant folding. Cast the result back to CallInst*
which is safe for these void AMX intrinsics that are never folded.
Co-Authored-By: Claude Sonnet 4.6 (1M context) <noreply@anthropic.com>
The multi-target runtime dispatcher selected a variant via a linear
ICMP_SGE walk over the Target::ISA enumerant, assuming each ISA is a
superset of all lower-numbered ones. Nova Lake (NVL) breaks that: it has
AVX10.2 (so it sorts above the AMX-bearing SPR/GNR tiers) but no AMX, so
an NVL system would mis-select an SPR/GNR variant and fault on AMX.
Replace the prior NVL-specific blocklist guard (systemISA != NVL) with a
requirement (allowlist): the AMX server tiers (SPR/GNR/DMR) require the
orthogonal "system has AMX" capability. Any non-AMX line -- NVL today,
future clients tomorrow -- fails that requirement with no dispatcher
change. Detection reads the same CPUID AMX bits get_x86_isa() uses to
separate the AMX tiers from NVL, and additionally gates on OS AMX tile
state (XCR0), mirroring how get_x86_isa() gates AVX/AVX512 on OS XSAVE
state -- on Linux AMX tile state is off until a process requests it via
prctl(ARCH_REQ_XCOMP_PERM). The check is exposed as a new __system_has_amx()
query alongside __get_system_best_isa(), and tools/check_isa.cpp reuses
the shared __os_has_amx_support() helper.
Co-Authored-By: Claude Opus 4.8 <noreply@anthropic.com>
Add the avx10.2nvl-x{4,8,16,32,64} x86 target family for Intel Nova Lake
(NVL). NVL implements AVX10.2 but, unlike Diamond Rapids (DMR), has no AMX.
It is therefore modeled as "DMR without AMX": its target hierarchy inherits
from ICL (avx512icl) rather than DMR/GNR, and none of the AMX capabilities
(AmxTile/AmxInt8/AmxBf16/AmxFp16) are advertised. The half-precision
rcp/rsqrt builtins are reused from the shared target-avx512fp16-x*-common.ll
files. The targets require LLVM >= 22 and are gated accordingly throughout.
dependabot[bot]