Release notes and docs for v1.31.0
This commit is contained in:
Arina Neshlyaeva
committed by
aneshlya
aneshlya
parent
0bf932e0af
commit
3db22a8845
@@ -1,3 +1,146 @@
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=== v1.31.0 === (25 June 2026)
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ISPC release featuring new avx10.2nvl targets for Intel Nova Lake processors,
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two new aggressive fast-math modes, expanded standard library math coverage
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(error, hyperbolic, and other functions), and several bug fixes. Based
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on LLVM 23 (pinned to commit 6be53ab).
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New Targets:
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* New `avx10.2nvl-x4`, `avx10.2nvl-x8`, `avx10.2nvl-x16`, `avx10.2nvl-x32`, and
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`avx10.2nvl-x64` targets have been added for Intel Nova Lake processors. These
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targets implement AVX10.2 and APX (Advanced Performance Extensions) but,
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unlike the `avx10.2dmr` (Diamond Rapids) targets, they do not include AMX. The
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corresponding predefined macro is `ISPC_TARGET_AVX10_2NVL`.
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Dispatcher:
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* The multi-target runtime dispatcher now selects an AMX-bearing server target
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variant (`avx512spr`, `avx512gnr`, `avx10.2dmr`) only when the system supports
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AMX, instead of relying solely on the ISA ordering. AMX support is checked the
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same way AVX-512 already is: the CPU must advertise the feature in CPUID and
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the OS must manage its XSAVE state.
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New Options:
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* A new `--opt=disable-apx[=<list>]` option allows disabling x86 APX (Advanced
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Performance Extensions) sub-features, which are enabled by default on
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APX-capable targets such as `avx10.2dmr` and `avx10.2nvl`. With no list it
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disables all APX sub-features; otherwise it accepts a comma-separated subset
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of `egpr`, `ndd`, `push2pop2`, `ppx`, `ccmp`, `cf`, `nf`, `zu`, and `jmpabs`.
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Windows x64 Stack Unwinding for APX:
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* On Windows x64, code that uses the APX extended general purpose registers
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(`egpr`, R16-R31) cannot be described by the legacy v1/v2 SEH unwind encodings,
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which have no register-number field for registers beyond R15. When targeting
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Windows on an APX-capable target (the `avx10.2dmr` and `avx10.2nvl` families)
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with `egpr` enabled, ISPC now automatically requests Windows x64 unwind
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information version 3, mirroring what Clang does. If you need compatibility
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with an older unwinder, disable the extended registers with
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`--opt=disable-apx=egpr`, which also drops the unwind v3 request.
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New Features:
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* Two new fast-math modes have been added: `balanced` and `aggressive`. These
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modes enable more aggressive optimizations compared to the default `legacy`
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mode, which was the mode provided in previous ISPC versions and is left
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unchanged. The fast-math mode can be selected with
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`--opt=fast-math:<mode>`.
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Standard Library:
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* **Breaking change**: `reduce_add()` now returns the same type as its input.
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Previously the signatures widened the result, but the implementation was
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inconsistent and partially incorrect. The new same-type convention matches
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the prevailing convention in other SIMD/SPMD ecosystems and is consistent
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with `reduce_min()` / `reduce_max()` in ISPC. For overflow-safe accumulation,
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cast the input to a wider type explicitly, e.g. `reduce_add((int32)x)` for an
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`int16` `x`. Any code that relied on the previous widened return type must be
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updated.
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* The Gauss error function `erf` and the complementary error function `erfc`
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have been added to the standard library.
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* The `expm1` function (computing `exp(x)-1` accurately) and the `log1p`
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function (computing `log(1+x)` accurately) have been added to the standard
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library.
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* The hyperbolic functions `sinh`, `cosh`, and `tanh` have been added to the
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standard library.
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* Improved the precision and performance of several existing math functions,
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including `asin` (especially close to 0), `acos`, `atan` (including correct
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`-0` handling and a new fast variant), and the default `log`.
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Experimental PowerPC 64-bit Support:
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* Initial support for the PowerPC 64-bit little-endian (ppc64le) architecture
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has been added using generic targets, along with native VSX targets (e.g.
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`vsx-i32x4`). The baseline is POWER ISA 2.7 (POWER8+) with VSX. This support
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is experimental and not included in official ISPC binaries. To use it, build
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ISPC from source with the `PPC64_ENABLED=ON` CMake option. Usage:
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`ispc --arch=ppc64le --target=vsx-i32x4 foo.ispc -o foo.o`.
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Performance:
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* Massively sped up 32-bit shuffles on the `avx2-i32x16` target and varying popcnt
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on the `avx2-i8x32`, `avx512skx-x32`, and `avx512skx-x64` targets
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Bug Fixes:
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* Fixed preprocessing of macros in `foreach` ranges without surrounding spaces,
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e.g. `foreach (i = 0...MAXI)` now expands `MAXI` correctly (#3809).
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* Fixed alignment handling for extern declarations and ensured uniform const
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arrays always get native vector alignment to prevent misaligned access
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violations.
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* Fixed `varying bool<N>` LLVM type to match the mask representation.
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* Extended the safe-to-blend analysis to cover struct members, so masked stores
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to struct fields are now lowered to load-blend-store instead of branchy masked
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store emulation. This improves codegen for struct assignments on targets
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without native masked stores, such as NEON and SSE4.
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Build System:
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* Updated default LLVM version to LLVM 23 (pinned to commit 6be53ab, ahead of
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the LLVM 23.1.0 release).
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* Added support for building with LLVM 22.1.
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* Dropped support for LLVM 18 and LLVM 19.
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Recommended versions of Runtime Dependencies when targeting GPU:
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Linux:
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- Intel(R) Graphics Compute Runtime
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https://github.com/intel/compute-runtime/releases/tag/25.13.33276.16
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- Level Zero Loader
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https://github.com/oneapi-src/level-zero/releases/tag/v1.20.2
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- Threading Building Blocks (TBB)
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Alternatively, you can use a validated gfx driver stack supporting Intel Arc(TM)
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available at https://dgpu-docs.intel.com/driver/installation.html
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Windows:
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- Intel(R) Graphics Windows(R) DCH Drivers 32.0.101.8250
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https://www.intel.com/content/www/us/en/download/785597/869290/intel-arc-graphics-windows.html
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- Level Zero Loader
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https://github.com/oneapi-src/level-zero/releases/tag/v1.20.2
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- OpenCL(TM) Offline Compiler (OCLOC)
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https://www.intel.com/content/www/us/en/developer/articles/tool/oneapi-standalone-components.html
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(this is needed for AoT compilation on Windows only)
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- Supported GPU platforms: Intel(R) Arc Graphics, 11th-13th Gen Intel(R) Core
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processor graphics
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Components revisions used in GPU-enabled build:
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- https://github.com/KhronosGroup/SPIRV-LLVM-Translator/commit/5b7e49f
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- https://github.com/intel/vc-intrinsics/commit/c9c1011
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- https://github.com/oneapi-src/level-zero/commit/v1.20.2
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- https://github.com/llvm/llvm-project/commit/6be53ab
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=== v1.30.0 === (04 February 2026)
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ISPC release featuring Intel AMX (Advanced Matrix Extensions) support in the
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+49
-46
@@ -261,56 +261,17 @@ of recent changes to the compiler.
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Updating ISPC Programs For Changes In ISPC 1.31.0
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-------------------------------------------------
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New Architecture Support:
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* Initial support for the PowerPC 64-bit little-endian (ppc64le) architecture
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has been added using generic targets (e.g., generic-i32x4). The baseline is
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POWER ISA 2.7 (POWER8+) with VSX. This support is experimental and not
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included in official ISPC binaries. To use it, build ISPC from source with
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the `PPC64_ENABLED=ON` CMake option. Usage: `ispc --arch=ppc64le
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--target=generic-i32x4 foo.ispc -o foo.o`.
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New Features:
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* Implementation of two new fast-math modes: ``balanced`` and ``aggressive``.
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These modes bring more aggressive optimizations compared to the default
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``legacy`` mode. The latter was the mode provided so far in previous ISPC
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versions. It is still available and left unchanged. The fast-math mode can be
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specified with the option ``--opt=fast-math:<mode>``. See the optimization
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settings section for more information about the new modes.
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Standard Library Changes:
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* **Breaking change**: ``reduce_add()`` now returns the same type as its
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input. Previously the signatures widened the result, but the
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implementation was inconsistent and partially incorrect. The new
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same-type convention also matches the prevailing convention in other
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SIMD/SPMD ecosystems and is consistent with ``reduce_min()`` /
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``reduce_max()`` in ISPC. For overflow-safe accumulation, cast the
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input to a wider type explicitly, e.g. ``reduce_add((int32)x)`` for an
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``int16`` ``x``. Any code that relied on the previous widened return
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type must be updated.
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* The Gauss error function ``erf`` and the complementary error function ``erfc``
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have been added to the standard library.
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* The ``expm1`` function (meant to compute ``exp(x)-1`` accurately), and the
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``log1p`` function (meant to compute ``log(1+x)`` accurately) have also been
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added to the standard library.
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* The hyperbolic functions ``sinh``, ``cosh`` and ``tanh`` have also been added
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to the standard library.
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ISPC Targets:
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* New ``avx10.2nvl-x4``, ``avx10.2nvl-x8``, ``avx10.2nvl-x16``,
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``avx10.2nvl-x32``, and ``avx10.2nvl-x64`` targets have been added for Intel
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Nova Lake processors. These targets implement AVX10.2 with full AVX-512
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support but, unlike the ``avx10.2dmr`` (Diamond Rapids) targets, they do not
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include AMX. The corresponding predefined macro is ``ISPC_TARGET_AVX10_2NVL``.
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Nova Lake processors. These targets implement AVX10.2 and APX (Advanced
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Performance Extensions) but, unlike the ``avx10.2dmr`` (Diamond Rapids)
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targets, they do not include AMX. The corresponding predefined macro is
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``ISPC_TARGET_AVX10_2NVL``.
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* The multi-target runtime dispatcher now selects an AMX-bearing server target
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variant (``avx512spr``, ``avx512gnr``, ``avx10.2dmr``) only when the system
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supports AMX, instead of relying solely on the ISA ordering. AMX support is
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checked the same way AVX-512 already is: the CPU must advertise the feature in
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CPUID and the OS must manage its XSAVE state.
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supports AMX, instead of relying solely on the ISA ordering.
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New Options:
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@@ -328,11 +289,53 @@ Windows x64 Stack Unwinding For APX:
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encodings, which have no register-number field for registers beyond R15.
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When targeting Windows on an APX-capable target (the ``avx10.2dmr`` and
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``avx10.2nvl`` families) with ``egpr`` enabled, ISPC now automatically
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requests Windows x64 unwind information version 3 by setting the
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``winx64-eh-unwind`` module flag, mirroring what Clang does. If you need
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requests Windows x64 unwind information version 3. If you need
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compatibility with an older unwinder, disable the extended registers with
|
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``--opt=disable-apx=egpr``, which also drops the unwind v3 request.
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New Features:
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* Implementation of two new fast-math modes: ``balanced`` and ``aggressive``.
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These modes bring more aggressive optimizations compared to the default
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``legacy`` mode. The latter was the mode provided so far in previous ISPC
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versions. It is still available and left unchanged. The fast-math mode can be
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specified with the option ``--opt=fast-math:<mode>``. See the optimization
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settings section for more information about the new modes.
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Standard Library Changes:
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* **Breaking change**: ``reduce_add()`` now returns the same type as its
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input. Previously the signatures widened the result, but the
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implementation was inconsistent and partially incorrect. The new
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same-type convention also matches the prevailing convention in other
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SIMD/SPMD ecosystems and is consistent with ``reduce_min()`` /
|
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``reduce_max()`` in ISPC. For overflow-safe accumulation, cast the
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input to a wider type explicitly, e.g. ``reduce_add((int32)x)`` for an
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``int16`` ``x``. Any code that relied on the previous widened return
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type must be updated.
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* The Gauss error function ``erf`` and the complementary error function ``erfc``
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have been added to the standard library.
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* The ``expm1`` function (meant to compute ``exp(x)-1`` accurately), and the
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``log1p`` function (meant to compute ``log(1+x)`` accurately) have also been
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added to the standard library.
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* The hyperbolic functions ``sinh``, ``cosh`` and ``tanh`` have also been added
|
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to the standard library.
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* The precision of several existing math functions has been improved, including
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``asin`` (especially close to 0), ``acos``, ``atan`` (which now also handles
|
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``-0`` correctly), and the default ``log``. As a result, the values these
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functions return may differ slightly from previous ISPC versions. Code that
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relies on bit-exact results (for example, golden-output comparisons) may need
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to update its expected values.
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New Architecture Support:
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* Initial support for the PowerPC 64-bit little-endian (ppc64le) architecture
|
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has been added using generic targets (e.g., generic-i32x4). The baseline is
|
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POWER ISA 2.7 (POWER8+) with VSX. This support is experimental and not
|
||||
included in official ISPC binaries. To use it, build ISPC from source with
|
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the ``PPC64_ENABLED=ON`` CMake option. Usage: ``ispc --arch=ppc64le
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--target=generic-i32x4 foo.ispc -o foo.o``.
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Updating ISPC Programs For Changes In ISPC 1.30.0
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-------------------------------------------------
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