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f6d673a514 |
@@ -190,6 +190,9 @@
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/* compile time determination of SIMD support */
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#if !defined(ZSTD_NO_INTRINSICS)
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# if defined(__AVX2__)
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# define ZSTD_ARCH_X86_AVX2
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# endif
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# if defined(__SSE2__) || defined(_M_AMD64) || (defined (_M_IX86) && defined(_M_IX86_FP) && (_M_IX86_FP >= 2))
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# define ZSTD_ARCH_X86_SSE2
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# endif
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@@ -197,9 +200,13 @@
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# define ZSTD_ARCH_ARM_NEON
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# endif
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#
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# if defined(ZSTD_ARCH_X86_AVX2)
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# include <immintrin.h>
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# endif
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# if defined(ZSTD_ARCH_X86_SSE2)
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# include <emmintrin.h>
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# elif defined(ZSTD_ARCH_ARM_NEON)
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# endif
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# if defined(ZSTD_ARCH_ARM_NEON)
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# include <arm_neon.h>
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# endif
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#endif
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@@ -1002,6 +1002,27 @@ ZSTD_row_getSSEMask(int nbChunks, const BYTE* const src, const BYTE tag, const U
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}
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#endif
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#if defined(ZSTD_ARCH_X86_AVX2)
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FORCE_INLINE_TEMPLATE ZSTD_VecMask
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ZSTD_row_getAVXMask(int nbChunks, const BYTE* const src, const BYTE tag, const U32 head)
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{
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if (nbChunks==1) return ZSTD_row_getSSEMask(1, src, tag, head);
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{ const __m256i comparisonMask = _mm256_set1_epi8((char)tag);
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int matches[2] = {0};
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int i;
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assert(nbChunks == 2 || nbChunks == 4);
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for (i=0; i<(nbChunks/2); i++) {
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const __m256i chunk = _mm256_loadu_si256((const __m256i*)(const void*)(src + 32*i));
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const __m256i equalMask = _mm256_cmpeq_epi8(chunk, comparisonMask);
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matches[i] = _mm256_movemask_epi8(equalMask);
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}
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if (nbChunks == 2) return ZSTD_rotateRight_U32((U32)matches[0], head);
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assert(nbChunks == 4);
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return ZSTD_rotateRight_U64((U64)matches[1] << 32 | (U64)matches[0], head);
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}
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}
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#endif
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/* Returns a ZSTD_VecMask (U32) that has the nth bit set to 1 if the newly-computed "tag" matches
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* the hash at the nth position in a row of the tagTable.
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* Each row is a circular buffer beginning at the value of "head". So we must rotate the "matches" bitfield
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@@ -1013,7 +1034,11 @@ ZSTD_row_getMatchMask(const BYTE* const tagRow, const BYTE tag, const U32 head,
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assert((rowEntries == 16) || (rowEntries == 32) || rowEntries == 64);
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assert(rowEntries <= ZSTD_ROW_HASH_MAX_ENTRIES);
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#if defined(ZSTD_ARCH_X86_SSE2)
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#if defined(ZSTD_ARCH_X86_AVX2)
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return ZSTD_row_getAVXMask(rowEntries / 16, src, tag, head);
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#elif defined(ZSTD_ARCH_X86_SSE2)
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return ZSTD_row_getSSEMask(rowEntries / 16, src, tag, head);
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