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Refactor: extract AVX512FP16 rcp/rsqrt builtins into shared common files

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This commit is contained in:
Arina Neshlyaeva
2026-06-09 09:24:37 -07:00
committed by aneshlya
parent e6b0c7a3a9
commit e31ad3ba1a
11 changed files with 233 additions and 208 deletions
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builtins/target-avx512fp16-x16-common.ll
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;; Copyright (c) 2016-2026, Intel Corporation
;;
;; SPDX-License-Identifier: BSD-3-Clause
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;; half precision rcp and rsqrt using native AVX512FP16 instructions
;; they will be invoked only when hardware support is available.
declare <8 x half> @llvm.x86.avx512fp16.mask.rcp.sh(<8 x half>, <8 x half>, <8 x half>, i8)
define half @__rcp_uniform_half(half) nounwind readonly alwaysinline {
%vec = insertelement <8 x half> undef, half %0, i32 0
%rcp = tail call <8 x half> @llvm.x86.avx512fp16.mask.rcp.sh(<8 x half> %vec, <8 x half> %vec, <8 x half> undef, i8 -1)
%ret = extractelement <8 x half> %rcp, i32 0
ret half %ret
}
declare <16 x half> @llvm.x86.avx512fp16.mask.rcp.ph.256(<16 x half>, <16 x half>, i16)
define <16 x half> @__rcp_varying_half(<16 x half>) nounwind readonly alwaysinline {
%ret = tail call <16 x half> @llvm.x86.avx512fp16.mask.rcp.ph.256(<16 x half> %0, <16 x half> undef, i16 -1)
ret <16 x half> %ret
}
declare <8 x half> @llvm.x86.avx512fp16.mask.rsqrt.sh(<8 x half>, <8 x half>, <8 x half>, i8)
define half @__rsqrt_uniform_half(half) nounwind readnone alwaysinline {
%vec = insertelement <8 x half> undef, half %0, i32 0
%rsqrt = tail call <8 x half> @llvm.x86.avx512fp16.mask.rsqrt.sh(<8 x half> %vec, <8 x half> %vec, <8 x half> undef, i8 -1)
%ret = extractelement <8 x half> %rsqrt, i32 0
ret half %ret
}
declare <16 x half> @llvm.x86.avx512fp16.mask.rsqrt.ph.256(<16 x half>, <16 x half>, i16)
define <16 x half> @__rsqrt_varying_half(<16 x half>) nounwind readnone alwaysinline {
%ret = tail call <16 x half> @llvm.x86.avx512fp16.mask.rsqrt.ph.256(<16 x half> %0, <16 x half> undef, i16 -1)
ret <16 x half> %ret
}
builtins/target-avx512fp16-x32-common.ll
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;; Copyright (c) 2020-2026, Intel Corporation
;;
;; SPDX-License-Identifier: BSD-3-Clause
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;; half precision rcp and rsqrt using native AVX512FP16 instructions
;; they will be invoked only when hardware support is available.
declare <8 x half> @llvm.x86.avx512fp16.mask.rcp.sh(<8 x half>, <8 x half>, <8 x half>, i8)
define half @__rcp_uniform_half(half) nounwind readonly alwaysinline {
%vec = insertelement <8 x half> undef, half %0, i32 0
%rcp = tail call <8 x half> @llvm.x86.avx512fp16.mask.rcp.sh(<8 x half> %vec, <8 x half> %vec, <8 x half> undef, i8 -1)
%ret = extractelement <8 x half> %rcp, i32 0
ret half %ret
}
declare <32 x half> @llvm.x86.avx512fp16.mask.rcp.ph.512(<32 x half>, <32 x half>, i32)
define <32 x half> @__rcp_varying_half(<32 x half>) nounwind readonly alwaysinline {
%ret = tail call <32 x half> @llvm.x86.avx512fp16.mask.rcp.ph.512(<32 x half> %0, <32 x half> undef, i32 -1)
ret <32 x half> %ret
}
declare <8 x half> @llvm.x86.avx512fp16.mask.rsqrt.sh(<8 x half>, <8 x half>, <8 x half>, i8)
define half @__rsqrt_uniform_half(half) nounwind readnone alwaysinline {
%vec = insertelement <8 x half> undef, half %0, i32 0
%rsqrt = tail call <8 x half> @llvm.x86.avx512fp16.mask.rsqrt.sh(<8 x half> %vec, <8 x half> %vec, <8 x half> undef, i8 -1)
%ret = extractelement <8 x half> %rsqrt, i32 0
ret half %ret
}
declare <32 x half> @llvm.x86.avx512fp16.mask.rsqrt.ph.512(<32 x half>, <32 x half>, i32)
define <32 x half> @__rsqrt_varying_half(<32 x half>) nounwind readnone alwaysinline {
%ret = tail call <32 x half> @llvm.x86.avx512fp16.mask.rsqrt.ph.512(<32 x half> %0, <32 x half> undef, i32 -1)
ret <32 x half> %ret
}
builtins/target-avx512fp16-x4-common.ll
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;; Copyright (c) 2016-2026, Intel Corporation
;;
;; SPDX-License-Identifier: BSD-3-Clause
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;; half precision rcp and rsqrt using native AVX512FP16 instructions
;; they will be invoked only when hardware support is available.
declare <8 x half> @llvm.x86.avx512fp16.mask.rcp.sh(<8 x half>, <8 x half>, <8 x half>, i8)
define half @__rcp_uniform_half(half) nounwind readonly alwaysinline {
%vec = insertelement <8 x half> undef, half %0, i32 0
%rcp = tail call <8 x half> @llvm.x86.avx512fp16.mask.rcp.sh(<8 x half> %vec, <8 x half> %vec, <8 x half> undef, i8 -1)
%ret = extractelement <8 x half> %rcp, i32 0
ret half %ret
}
declare <8 x half> @llvm.x86.avx512fp16.mask.rcp.ph.128(<8 x half>, <8 x half>, i8)
define <4 x half> @__rcp_varying_half(<4 x half>) nounwind readonly alwaysinline {
%vec = shufflevector <4 x half> %0, <4 x half> undef,
<8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 undef, i32 undef, i32 undef, i32 undef>
%rcp = tail call <8 x half> @llvm.x86.avx512fp16.mask.rcp.ph.128(<8 x half> %vec, <8 x half> undef, i8 -1)
%ret = shufflevector <8 x half> %rcp, <8 x half> undef,
<4 x i32> <i32 0, i32 1, i32 2, i32 3>
ret <4 x half> %ret
}
declare <8 x half> @llvm.x86.avx512fp16.mask.rsqrt.sh(<8 x half>, <8 x half>, <8 x half>, i8)
define half @__rsqrt_uniform_half(half) nounwind readnone alwaysinline {
%vec = insertelement <8 x half> undef, half %0, i32 0
%rsqrt = tail call <8 x half> @llvm.x86.avx512fp16.mask.rsqrt.sh(<8 x half> %vec, <8 x half> %vec, <8 x half> undef, i8 -1)
%ret = extractelement <8 x half> %rsqrt, i32 0
ret half %ret
}
declare <8 x half> @llvm.x86.avx512fp16.mask.rsqrt.ph.128(<8 x half>, <8 x half>, i8)
define <4 x half> @__rsqrt_varying_half(<4 x half>) nounwind readnone alwaysinline {
%vec = shufflevector <4 x half> %0, <4 x half> undef,
<8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 undef, i32 undef, i32 undef, i32 undef>
%rsqrt = tail call <8 x half> @llvm.x86.avx512fp16.mask.rsqrt.ph.128(<8 x half> %vec, <8 x half> undef, i8 -1)
%ret = shufflevector <8 x half> %rsqrt, <8 x half> undef,
<4 x i32> <i32 0, i32 1, i32 2, i32 3>
ret <4 x half> %ret
}
builtins/target-avx512fp16-x64-common.ll
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;; Copyright (c) 2020-2026, Intel Corporation
;;
;; SPDX-License-Identifier: BSD-3-Clause
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;; half precision rcp and rsqrt using native AVX512FP16 instructions
;; they will be invoked only when hardware support is available.
declare <8 x half> @llvm.x86.avx512fp16.mask.rcp.sh(<8 x half>, <8 x half>, <8 x half>, i8)
define half @__rcp_uniform_half(half) nounwind readonly alwaysinline {
%vec = insertelement <8 x half> undef, half %0, i32 0
%rcp = tail call <8 x half> @llvm.x86.avx512fp16.mask.rcp.sh(<8 x half> %vec, <8 x half> %vec, <8 x half> undef, i8 -1)
%ret = extractelement <8 x half> %rcp, i32 0
ret half %ret
}
declare <32 x half> @llvm.x86.avx512fp16.mask.rcp.ph.512(<32 x half>, <32 x half>, i32)
define <64 x half> @__rcp_varying_half(<64 x half>) nounwind readonly alwaysinline {
%vec1 = shufflevector <64 x half> %0, <64 x half> undef,
<32 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7,
i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15,
i32 16, i32 17, i32 18, i32 19, i32 20, i32 21, i32 22, i32 23,
i32 24, i32 25, i32 26, i32 27, i32 28, i32 29, i32 30, i32 31>
%vec2 = shufflevector <64 x half> %0, <64 x half> undef,
<32 x i32> <i32 32, i32 33, i32 34, i32 35, i32 36, i32 37, i32 38, i32 39,
i32 40, i32 41, i32 42, i32 43, i32 44, i32 45, i32 46, i32 47,
i32 48, i32 49, i32 50, i32 51, i32 52, i32 53, i32 54, i32 55,
i32 56, i32 57, i32 58, i32 59, i32 60, i32 61, i32 62, i32 63>
%rcp1 = tail call <32 x half> @llvm.x86.avx512fp16.mask.rcp.ph.512(<32 x half> %vec1, <32 x half> undef, i32 -1)
%rcp2 = tail call <32 x half> @llvm.x86.avx512fp16.mask.rcp.ph.512(<32 x half> %vec2, <32 x half> undef, i32 -1)
%ret = shufflevector <32 x half> %rcp1, <32 x half> %rcp2,
<64 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7,
i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15,
i32 16, i32 17, i32 18, i32 19, i32 20, i32 21, i32 22, i32 23,
i32 24, i32 25, i32 26, i32 27, i32 28, i32 29, i32 30, i32 31,
i32 32, i32 33, i32 34, i32 35, i32 36, i32 37, i32 38, i32 39,
i32 40, i32 41, i32 42, i32 43, i32 44, i32 45, i32 46, i32 47,
i32 48, i32 49, i32 50, i32 51, i32 52, i32 53, i32 54, i32 55,
i32 56, i32 57, i32 58, i32 59, i32 60, i32 61, i32 62, i32 63>
ret <64 x half> %ret
}
declare <8 x half> @llvm.x86.avx512fp16.mask.rsqrt.sh(<8 x half>, <8 x half>, <8 x half>, i8)
define half @__rsqrt_uniform_half(half) nounwind readnone alwaysinline {
%vec = insertelement <8 x half> undef, half %0, i32 0
%rsqrt = tail call <8 x half> @llvm.x86.avx512fp16.mask.rsqrt.sh(<8 x half> %vec, <8 x half> %vec, <8 x half> undef, i8 -1)
%ret = extractelement <8 x half> %rsqrt, i32 0
ret half %ret
}
declare <32 x half> @llvm.x86.avx512fp16.mask.rsqrt.ph.512(<32 x half>, <32 x half>, i32)
define <64 x half> @__rsqrt_varying_half(<64 x half>) nounwind readnone alwaysinline {
%vec1 = shufflevector <64 x half> %0, <64 x half> undef,
<32 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7,
i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15,
i32 16, i32 17, i32 18, i32 19, i32 20, i32 21, i32 22, i32 23,
i32 24, i32 25, i32 26, i32 27, i32 28, i32 29, i32 30, i32 31>
%vec2 = shufflevector <64 x half> %0, <64 x half> undef,
<32 x i32> <i32 32, i32 33, i32 34, i32 35, i32 36, i32 37, i32 38, i32 39,
i32 40, i32 41, i32 42, i32 43, i32 44, i32 45, i32 46, i32 47,
i32 48, i32 49, i32 50, i32 51, i32 52, i32 53, i32 54, i32 55,
i32 56, i32 57, i32 58, i32 59, i32 60, i32 61, i32 62, i32 63>
%rsqrt1 = tail call <32 x half> @llvm.x86.avx512fp16.mask.rsqrt.ph.512(<32 x half> %vec1, <32 x half> undef, i32 -1)
%rsqrt2 = tail call <32 x half> @llvm.x86.avx512fp16.mask.rsqrt.ph.512(<32 x half> %vec2, <32 x half> undef, i32 -1)
%ret = shufflevector <32 x half> %rsqrt1, <32 x half> %rsqrt2,
<64 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7,
i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15,
i32 16, i32 17, i32 18, i32 19, i32 20, i32 21, i32 22, i32 23,
i32 24, i32 25, i32 26, i32 27, i32 28, i32 29, i32 30, i32 31,
i32 32, i32 33, i32 34, i32 35, i32 36, i32 37, i32 38, i32 39,
i32 40, i32 41, i32 42, i32 43, i32 44, i32 45, i32 46, i32 47,
i32 48, i32 49, i32 50, i32 51, i32 52, i32 53, i32 54, i32 55,
i32 56, i32 57, i32 58, i32 59, i32 60, i32 61, i32 62, i32 63>
ret <64 x half> %ret
}
builtins/target-avx512fp16-x8-common.ll
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;; Copyright (c) 2016-2026, Intel Corporation
;;
;; SPDX-License-Identifier: BSD-3-Clause
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;; half precision rcp and rsqrt using native AVX512FP16 instructions
;; they will be invoked only when hardware support is available.
declare <8 x half> @llvm.x86.avx512fp16.mask.rcp.sh(<8 x half>, <8 x half>, <8 x half>, i8)
define half @__rcp_uniform_half(half) nounwind readonly alwaysinline {
%vec = insertelement <8 x half> undef, half %0, i32 0
%rcp = tail call <8 x half> @llvm.x86.avx512fp16.mask.rcp.sh(<8 x half> %vec, <8 x half> %vec, <8 x half> undef, i8 -1)
%ret = extractelement <8 x half> %rcp, i32 0
ret half %ret
}
declare <8 x half> @llvm.x86.avx512fp16.mask.rcp.ph.128(<8 x half>, <8 x half>, i8)
define <8 x half> @__rcp_varying_half(<8 x half>) nounwind readonly alwaysinline {
%ret = tail call <8 x half> @llvm.x86.avx512fp16.mask.rcp.ph.128(<8 x half> %0, <8 x half> undef, i8 -1)
ret <8 x half> %ret
}
declare <8 x half> @llvm.x86.avx512fp16.mask.rsqrt.sh(<8 x half>, <8 x half>, <8 x half>, i8)
define half @__rsqrt_uniform_half(half) nounwind readnone alwaysinline {
%vec = insertelement <8 x half> undef, half %0, i32 0
%rsqrt = tail call <8 x half> @llvm.x86.avx512fp16.mask.rsqrt.sh(<8 x half> %vec, <8 x half> %vec, <8 x half> undef, i8 -1)
%ret = extractelement <8 x half> %rsqrt, i32 0
ret half %ret
}
declare <8 x half> @llvm.x86.avx512fp16.mask.rsqrt.ph.128(<8 x half>, <8 x half>, i8)
define <8 x half> @__rsqrt_varying_half(<8 x half>) nounwind readnone alwaysinline {
%ret = tail call <8 x half> @llvm.x86.avx512fp16.mask.rsqrt.ph.128(<8 x half> %0, <8 x half> undef, i8 -1)
ret <8 x half> %ret
}
builtins/target-avx512spr-x16.ll
+1 -32
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@@ -6,35 +6,4 @@ define(`WIDTH',`16')
define(`ISA',`AVX512SKX')
include(`target-avx512spr-amx-utils.ll')
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;; half precision rcp and rsqrt using native SPR instriuctions
;; they will be invoked only when hardware support is available.
declare <8 x half> @llvm.x86.avx512fp16.mask.rcp.sh(<8 x half>, <8 x half>, <8 x half>, i8)
define half @__rcp_uniform_half(half) nounwind readonly alwaysinline {
%vec = insertelement <8 x half> undef, half %0, i32 0
%rcp = tail call <8 x half> @llvm.x86.avx512fp16.mask.rcp.sh(<8 x half> %vec, <8 x half> %vec, <8 x half> undef, i8 -1)
%ret = extractelement <8 x half> %rcp, i32 0
ret half %ret
}
declare <16 x half> @llvm.x86.avx512fp16.mask.rcp.ph.256(<16 x half>, <16 x half>, i16)
define <16 x half> @__rcp_varying_half(<16 x half>) nounwind readonly alwaysinline {
%ret = tail call <16 x half> @llvm.x86.avx512fp16.mask.rcp.ph.256(<16 x half> %0, <16 x half> undef, i16 -1)
ret <16 x half> %ret
}
declare <8 x half> @llvm.x86.avx512fp16.mask.rsqrt.sh(<8 x half>, <8 x half>, <8 x half>, i8)
define half @__rsqrt_uniform_half(half) nounwind readnone alwaysinline {
%vec = insertelement <8 x half> undef, half %0, i32 0
%rsqrt = tail call <8 x half> @llvm.x86.avx512fp16.mask.rsqrt.sh(<8 x half> %vec, <8 x half> %vec, <8 x half> undef, i8 -1)
%ret = extractelement <8 x half> %rsqrt, i32 0
ret half %ret
}
declare <16 x half> @llvm.x86.avx512fp16.mask.rsqrt.ph.256(<16 x half>, <16 x half>, i16)
define <16 x half> @__rsqrt_varying_half(<16 x half>) nounwind readnone alwaysinline {
%ret = tail call <16 x half> @llvm.x86.avx512fp16.mask.rsqrt.ph.256(<16 x half> %0, <16 x half> undef, i16 -1)
ret <16 x half> %ret
}
include(`target-avx512fp16-x16-common.ll')
builtins/target-avx512spr-x32.ll
+1 -32
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@@ -6,35 +6,4 @@ define(`WIDTH',`32')
define(`ISA',`AVX512SKX')
include(`target-avx512spr-amx-utils.ll')
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;; half precision rcp and rsqrt using native SPR instriuctions
;; they will be invoked only when hardware support is available.
declare <8 x half> @llvm.x86.avx512fp16.mask.rcp.sh(<8 x half>, <8 x half>, <8 x half>, i8)
define half @__rcp_uniform_half(half) nounwind readonly alwaysinline {
%vec = insertelement <8 x half> undef, half %0, i32 0
%rcp = tail call <8 x half> @llvm.x86.avx512fp16.mask.rcp.sh(<8 x half> %vec, <8 x half> %vec, <8 x half> undef, i8 -1)
%ret = extractelement <8 x half> %rcp, i32 0
ret half %ret
}
declare <32 x half> @llvm.x86.avx512fp16.mask.rcp.ph.512(<32 x half>, <32 x half>, i32)
define <32 x half> @__rcp_varying_half(<32 x half>) nounwind readonly alwaysinline {
%ret = tail call <32 x half> @llvm.x86.avx512fp16.mask.rcp.ph.512(<32 x half> %0, <32 x half> undef, i32 -1)
ret <32 x half> %ret
}
declare <8 x half> @llvm.x86.avx512fp16.mask.rsqrt.sh(<8 x half>, <8 x half>, <8 x half>, i8)
define half @__rsqrt_uniform_half(half) nounwind readnone alwaysinline {
%vec = insertelement <8 x half> undef, half %0, i32 0
%rsqrt = tail call <8 x half> @llvm.x86.avx512fp16.mask.rsqrt.sh(<8 x half> %vec, <8 x half> %vec, <8 x half> undef, i8 -1)
%ret = extractelement <8 x half> %rsqrt, i32 0
ret half %ret
}
declare <32 x half> @llvm.x86.avx512fp16.mask.rsqrt.ph.512(<32 x half>, <32 x half>, i32)
define <32 x half> @__rsqrt_varying_half(<32 x half>) nounwind readnone alwaysinline {
%ret = tail call <32 x half> @llvm.x86.avx512fp16.mask.rsqrt.ph.512(<32 x half> %0, <32 x half> undef, i32 -1)
ret <32 x half> %ret
}
include(`target-avx512fp16-x32-common.ll')
builtins/target-avx512spr-x4.ll
+1 -40
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@@ -6,43 +6,4 @@ define(`WIDTH',`4')
define(`ISA',`AVX512SKX')
include(`target-avx512spr-amx-utils.ll')
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;; half precision rcp and rsqrt using native SPR instriuctions
;; they will be invoked only when hardware support is available.
declare <8 x half> @llvm.x86.avx512fp16.mask.rcp.sh(<8 x half>, <8 x half>, <8 x half>, i8)
define half @__rcp_uniform_half(half) nounwind readonly alwaysinline {
%vec = insertelement <8 x half> undef, half %0, i32 0
%rcp = tail call <8 x half> @llvm.x86.avx512fp16.mask.rcp.sh(<8 x half> %vec, <8 x half> %vec, <8 x half> undef, i8 -1)
%ret = extractelement <8 x half> %rcp, i32 0
ret half %ret
}
declare <8 x half> @llvm.x86.avx512fp16.mask.rcp.ph.128(<8 x half>, <8 x half>, i8)
define <4 x half> @__rcp_varying_half(<4 x half>) nounwind readonly alwaysinline {
%vec = shufflevector <4 x half> %0, <4 x half> undef,
<8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 undef, i32 undef, i32 undef, i32 undef>
%rcp = tail call <8 x half> @llvm.x86.avx512fp16.mask.rcp.ph.128(<8 x half> %vec, <8 x half> undef, i8 -1)
%ret = shufflevector <8 x half> %rcp, <8 x half> undef,
<4 x i32> <i32 0, i32 1, i32 2, i32 3>
ret <4 x half> %ret
}
declare <8 x half> @llvm.x86.avx512fp16.mask.rsqrt.sh(<8 x half>, <8 x half>, <8 x half>, i8)
define half @__rsqrt_uniform_half(half) nounwind readnone alwaysinline {
%vec = insertelement <8 x half> undef, half %0, i32 0
%rsqrt = tail call <8 x half> @llvm.x86.avx512fp16.mask.rsqrt.sh(<8 x half> %vec, <8 x half> %vec, <8 x half> undef, i8 -1)
%ret = extractelement <8 x half> %rsqrt, i32 0
ret half %ret
}
declare <8 x half> @llvm.x86.avx512fp16.mask.rsqrt.ph.128(<8 x half>, <8 x half>, i8)
define <4 x half> @__rsqrt_varying_half(<4 x half>) nounwind readnone alwaysinline {
%vec = shufflevector <4 x half> %0, <4 x half> undef,
<8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 undef, i32 undef, i32 undef, i32 undef>
%rsqrt = tail call <8 x half> @llvm.x86.avx512fp16.mask.rsqrt.ph.128(<8 x half> %vec, <8 x half> undef, i8 -1)
%ret = shufflevector <8 x half> %rsqrt, <8 x half> undef,
<4 x i32> <i32 0, i32 1, i32 2, i32 3>
ret <4 x half> %ret
}
include(`target-avx512fp16-x4-common.ll')
builtins/target-avx512spr-x64.ll
+1 -72
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@@ -6,75 +6,4 @@ define(`WIDTH',`64')
define(`ISA',`AVX512SKX')
include(`target-avx512spr-amx-utils.ll')
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;; half precision rcp and rsqrt using native SPR instriuctions
;; they will be invoked only when hardware support is available.
declare <8 x half> @llvm.x86.avx512fp16.mask.rcp.sh(<8 x half>, <8 x half>, <8 x half>, i8)
define half @__rcp_uniform_half(half) nounwind readonly alwaysinline {
%vec = insertelement <8 x half> undef, half %0, i32 0
%rcp = tail call <8 x half> @llvm.x86.avx512fp16.mask.rcp.sh(<8 x half> %vec, <8 x half> %vec, <8 x half> undef, i8 -1)
%ret = extractelement <8 x half> %rcp, i32 0
ret half %ret
}
declare <32 x half> @llvm.x86.avx512fp16.mask.rcp.ph.512(<32 x half>, <32 x half>, i32)
define <64 x half> @__rcp_varying_half(<64 x half>) nounwind readonly alwaysinline {
%vec1 = shufflevector <64 x half> %0, <64 x half> undef,
<32 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7,
i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15,
i32 16, i32 17, i32 18, i32 19, i32 20, i32 21, i32 22, i32 23,
i32 24, i32 25, i32 26, i32 27, i32 28, i32 29, i32 30, i32 31>
%vec2 = shufflevector <64 x half> %0, <64 x half> undef,
<32 x i32> <i32 32, i32 33, i32 34, i32 35, i32 36, i32 37, i32 38, i32 39,
i32 40, i32 41, i32 42, i32 43, i32 44, i32 45, i32 46, i32 47,
i32 48, i32 49, i32 50, i32 51, i32 52, i32 53, i32 54, i32 55,
i32 56, i32 57, i32 58, i32 59, i32 60, i32 61, i32 62, i32 63>
%rcp1 = tail call <32 x half> @llvm.x86.avx512fp16.mask.rcp.ph.512(<32 x half> %vec1, <32 x half> undef, i32 -1)
%rcp2 = tail call <32 x half> @llvm.x86.avx512fp16.mask.rcp.ph.512(<32 x half> %vec2, <32 x half> undef, i32 -1)
%ret = shufflevector <32 x half> %rcp1, <32 x half> %rcp2,
<64 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7,
i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15,
i32 16, i32 17, i32 18, i32 19, i32 20, i32 21, i32 22, i32 23,
i32 24, i32 25, i32 26, i32 27, i32 28, i32 29, i32 30, i32 31,
i32 32, i32 33, i32 34, i32 35, i32 36, i32 37, i32 38, i32 39,
i32 40, i32 41, i32 42, i32 43, i32 44, i32 45, i32 46, i32 47,
i32 48, i32 49, i32 50, i32 51, i32 52, i32 53, i32 54, i32 55,
i32 56, i32 57, i32 58, i32 59, i32 60, i32 61, i32 62, i32 63>
ret <64 x half> %ret
}
declare <8 x half> @llvm.x86.avx512fp16.mask.rsqrt.sh(<8 x half>, <8 x half>, <8 x half>, i8)
define half @__rsqrt_uniform_half(half) nounwind readnone alwaysinline {
%vec = insertelement <8 x half> undef, half %0, i32 0
%rsqrt = tail call <8 x half> @llvm.x86.avx512fp16.mask.rsqrt.sh(<8 x half> %vec, <8 x half> %vec, <8 x half> undef, i8 -1)
%ret = extractelement <8 x half> %rsqrt, i32 0
ret half %ret
}
declare <32 x half> @llvm.x86.avx512fp16.mask.rsqrt.ph.512(<32 x half>, <32 x half>, i32)
define <64 x half> @__rsqrt_varying_half(<64 x half>) nounwind readnone alwaysinline {
%vec1 = shufflevector <64 x half> %0, <64 x half> undef,
<32 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7,
i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15,
i32 16, i32 17, i32 18, i32 19, i32 20, i32 21, i32 22, i32 23,
i32 24, i32 25, i32 26, i32 27, i32 28, i32 29, i32 30, i32 31>
%vec2 = shufflevector <64 x half> %0, <64 x half> undef,
<32 x i32> <i32 32, i32 33, i32 34, i32 35, i32 36, i32 37, i32 38, i32 39,
i32 40, i32 41, i32 42, i32 43, i32 44, i32 45, i32 46, i32 47,
i32 48, i32 49, i32 50, i32 51, i32 52, i32 53, i32 54, i32 55,
i32 56, i32 57, i32 58, i32 59, i32 60, i32 61, i32 62, i32 63>
%rsqrt1 = tail call <32 x half> @llvm.x86.avx512fp16.mask.rsqrt.ph.512(<32 x half> %vec1, <32 x half> undef, i32 -1)
%rsqrt2 = tail call <32 x half> @llvm.x86.avx512fp16.mask.rsqrt.ph.512(<32 x half> %vec2, <32 x half> undef, i32 -1)
%ret = shufflevector <32 x half> %rsqrt1, <32 x half> %rsqrt2,
<64 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7,
i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15,
i32 16, i32 17, i32 18, i32 19, i32 20, i32 21, i32 22, i32 23,
i32 24, i32 25, i32 26, i32 27, i32 28, i32 29, i32 30, i32 31,
i32 32, i32 33, i32 34, i32 35, i32 36, i32 37, i32 38, i32 39,
i32 40, i32 41, i32 42, i32 43, i32 44, i32 45, i32 46, i32 47,
i32 48, i32 49, i32 50, i32 51, i32 52, i32 53, i32 54, i32 55,
i32 56, i32 57, i32 58, i32 59, i32 60, i32 61, i32 62, i32 63>
ret <64 x half> %ret
}
include(`target-avx512fp16-x64-common.ll')
builtins/target-avx512spr-x8.ll
+1 -32
View File
@@ -6,35 +6,4 @@ define(`WIDTH',`8')
define(`ISA',`AVX512SKX')
include(`target-avx512spr-amx-utils.ll')
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;; half precision rcp and rsqrt using native SPR instriuctions
;; they will be invoked only when hardware support is available.
declare <8 x half> @llvm.x86.avx512fp16.mask.rcp.sh(<8 x half>, <8 x half>, <8 x half>, i8)
define half @__rcp_uniform_half(half) nounwind readonly alwaysinline {
%vec = insertelement <8 x half> undef, half %0, i32 0
%rcp = tail call <8 x half> @llvm.x86.avx512fp16.mask.rcp.sh(<8 x half> %vec, <8 x half> %vec, <8 x half> undef, i8 -1)
%ret = extractelement <8 x half> %rcp, i32 0
ret half %ret
}
declare <8 x half> @llvm.x86.avx512fp16.mask.rcp.ph.128(<8 x half>, <8 x half>, i8)
define <8 x half> @__rcp_varying_half(<8 x half>) nounwind readonly alwaysinline {
%ret = tail call <8 x half> @llvm.x86.avx512fp16.mask.rcp.ph.128(<8 x half> %0, <8 x half> undef, i8 -1)
ret <8 x half> %ret
}
declare <8 x half> @llvm.x86.avx512fp16.mask.rsqrt.sh(<8 x half>, <8 x half>, <8 x half>, i8)
define half @__rsqrt_uniform_half(half) nounwind readnone alwaysinline {
%vec = insertelement <8 x half> undef, half %0, i32 0
%rsqrt = tail call <8 x half> @llvm.x86.avx512fp16.mask.rsqrt.sh(<8 x half> %vec, <8 x half> %vec, <8 x half> undef, i8 -1)
%ret = extractelement <8 x half> %rsqrt, i32 0
ret half %ret
}
declare <8 x half> @llvm.x86.avx512fp16.mask.rsqrt.ph.128(<8 x half>, <8 x half>, i8)
define <8 x half> @__rsqrt_varying_half(<8 x half>) nounwind readnone alwaysinline {
%ret = tail call <8 x half> @llvm.x86.avx512fp16.mask.rsqrt.ph.128(<8 x half> %0, <8 x half> undef, i8 -1)
ret <8 x half> %ret
}
include(`target-avx512fp16-x8-common.ll')
cmake/GenerateBuiltins.cmake
+5
View File
@@ -47,6 +47,11 @@ list(APPEND M4_IMPLICIT_DEPENDENCIES
builtins/target-avx-utils.ll
builtins/target-avx512-utils.ll
builtins/target-avx512spr-amx-utils.ll
builtins/target-avx512fp16-x4-common.ll
builtins/target-avx512fp16-x8-common.ll
builtins/target-avx512fp16-x16-common.ll
builtins/target-avx512fp16-x32-common.ll
builtins/target-avx512fp16-x64-common.ll
builtins/target-neon-common.ll
builtins/target-sse2-common.ll
builtins/target-sse4-common.ll