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SYCL: add support for WCL, NVL, CRI

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This commit is contained in:
Attila Afra
2025-11-24 22:11:36 +02:00
parent dc8e6ea8ad
commit 9921a85516
6 changed files with 28 additions and 13 deletions
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CHANGELOG.md
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@@ -1,6 +1,7 @@
Version History
---------------
- Added Intel BMG-G31, Wildcat Lake, Nova Lake, and Crescent Island GPU support
- Added AMD RDNA 3.5 GPU support, extended RDNA 2 support
### Changes in v2.3.3:
devices/sycl/sycl_device.cpp
+13 -10
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@@ -211,6 +211,7 @@ OIDN_NAMESPACE_BEGIN
case SYCLArch::Xe2LPG: score = 11; break;
case SYCLArch::Xe2HPG: score = 21; break;
case SYCLArch::Xe3LPG: score = 12; break;
case SYCLArch::Xe3pXPC: score = 31; break;
default:
return -1;
}
@@ -324,16 +325,17 @@ OIDN_NAMESPACE_BEGIN
std::cout << " Arch : ";
switch (arch)
{
case SYCLArch::XeLP: std::cout << "Xe-LP"; break;
case SYCLArch::XeLPG: std::cout << "Xe-LPG"; break;
case SYCLArch::XeLPGplus: std::cout << "Xe-LPG+"; break;
case SYCLArch::XeHPG: std::cout << "Xe-HPG"; break;
case SYCLArch::XeHPC: std::cout << "Xe-HPC"; break;
case SYCLArch::XeHPC_NoDPAS: std::cout << "Xe-HPC"; break;
case SYCLArch::Xe2LPG: std::cout << "Xe2-LPG"; break;
case SYCLArch::Xe2HPG: std::cout << "Xe2-HPG"; break;
case SYCLArch::Xe3LPG: std::cout << "Xe3-LPG"; break;
default: std::cout << "Unknown"; break;
case SYCLArch::XeLP: std::cout << "Xe-LP"; break;
case SYCLArch::XeLPG: std::cout << "Xe-LPG"; break;
case SYCLArch::XeLPGplus: std::cout << "Xe-LPG+"; break;
case SYCLArch::XeHPG: std::cout << "Xe-HPG"; break;
case SYCLArch::XeHPC: std::cout << "Xe-HPC"; break;
case SYCLArch::XeHPC_NoDPAS: std::cout << "Xe-HPC"; break;
case SYCLArch::Xe2LPG: std::cout << "Xe2-LPG"; break;
case SYCLArch::Xe2HPG: std::cout << "Xe2-HPG"; break;
case SYCLArch::Xe3LPG: std::cout << "Xe3-LPG"; break;
case SYCLArch::Xe3pXPC: std::cout << "Xe3p-XPC"; break;
default: std::cout << "Unknown"; break;
}
std::cout << std::endl;
@@ -369,6 +371,7 @@ OIDN_NAMESPACE_BEGIN
case SYCLArch::Xe2LPG:
case SYCLArch::Xe2HPG:
case SYCLArch::Xe3LPG:
case SYCLArch::Xe3pXPC:
weightDataType = DataType::Float16;
weightLayout = TensorLayout::OIhw8i16o2i;
break;
devices/sycl/sycl_device.h
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@@ -23,6 +23,7 @@ OIDN_NAMESPACE_BEGIN
Xe2LPG,
Xe2HPG,
Xe3LPG,
Xe3pXPC,
};
class SYCLPhysicalDevice : public PhysicalDevice
devices/sycl/sycl_device_table.h
+10 -1
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@@ -77,7 +77,7 @@ OIDN_NAMESPACE_BEGIN
SYCLArch::Xe2HPG,
{
0x05004000, // bmg-g21
0x05008000,
0x05008000, // bmg-g31
}
},
{
@@ -85,8 +85,17 @@ OIDN_NAMESPACE_BEGIN
{
0x07800000, // ptl-h
0x07804000, // ptl-u
0x0780c000, // wcl
0x07810000, // nvl-s
0x07814000, // nvl-u
}
},
{
SYCLArch::Xe3pXPC,
{
0x08c2c000, // cri
}
}
};
OIDN_NAMESPACE_END
devices/sycl/sycl_engine.cpp
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@@ -61,6 +61,7 @@ OIDN_NAMESPACE_BEGIN
case SYCLArch::Xe2LPG:
case SYCLArch::Xe2HPG:
case SYCLArch::Xe3LPG:
case SYCLArch::Xe3pXPC:
return xe2::newSYCLConv(this, desc);
default:
throw std::logic_error("unsupported architecture");
doc/overview.md
+2 -2
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@@ -48,8 +48,8 @@ vendors:
Intel® Data Center GPU Max Series, Intel® Iris® Xe Graphics, Intel® Core™
Ultra Processors with Intel® Arc™ Graphics, 11th-14th Gen Intel® Core™
processor graphics, and related Intel Pentium® and Celeron® processors
(Xe-LP, Xe-LPG, Xe-LPG+, Xe-HPG, Xe-HPC, Xe2-LPG, Xe2-HPG, and Xe3-LPG
microarchitectures)
(Xe-LP, Xe-LPG, Xe-LPG+, Xe-HPG, Xe-HPC, Xe2-LPG, Xe2-HPG, Xe3-LPG, and
Xe3p-XPC microarchitectures)
- NVIDIA GPUs with Volta, Turing, Ampere, Ada Lovelace, Hopper, and
Blackwell architectures