The multi-target runtime dispatcher selected a variant via a linear
ICMP_SGE walk over the Target::ISA enumerant, assuming each ISA is a
superset of all lower-numbered ones. Nova Lake (NVL) breaks that: it has
AVX10.2 (so it sorts above the AMX-bearing SPR/GNR tiers) but no AMX, so
an NVL system would mis-select an SPR/GNR variant and fault on AMX.
Replace the prior NVL-specific blocklist guard (systemISA != NVL) with a
requirement (allowlist): the AMX server tiers (SPR/GNR/DMR) require the
orthogonal "system has AMX" capability. Any non-AMX line -- NVL today,
future clients tomorrow -- fails that requirement with no dispatcher
change. Detection reads the same CPUID AMX bits get_x86_isa() uses to
separate the AMX tiers from NVL, and additionally gates on OS AMX tile
state (XCR0), mirroring how get_x86_isa() gates AVX/AVX512 on OS XSAVE
state -- on Linux AMX tile state is off until a process requests it via
prctl(ARCH_REQ_XCOMP_PERM). The check is exposed as a new __system_has_amx()
query alongside __get_system_best_isa(), and tools/check_isa.cpp reuses
the shared __os_has_amx_support() helper.
Co-Authored-By: Claude Opus 4.8 <noreply@anthropic.com>
