Files
ispc/builtins/target-avx512fp16-x4-common.ll
azwolskiandClaude Sonnet 4.6 6e021c57e5 Fix #3782: Migrate builtins IR and M4 macros to use poison instead of undef (#3825)
Replace all occurrences of the deprecated undef keyword with poison in ISPC's
built-in IR library files (builtins/*.ll) and M4 macro files
(builtins/util.m4, builtins/util-xe.m4, builtins/svml.m4).

Co-Authored-By: Claude Sonnet 4.6 <noreply@anthropic.com>
2026-06-23 09:10:35 -07:00

44 lines
2.3 KiB
LLVM

;; Copyright (c) 2016-2026, Intel Corporation
;;
;; SPDX-License-Identifier: BSD-3-Clause
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;; half precision rcp and rsqrt using native AVX512FP16 instructions
;; they will be invoked only when hardware support is available.
declare <8 x half> @llvm.x86.avx512fp16.mask.rcp.sh(<8 x half>, <8 x half>, <8 x half>, i8)
define half @__rcp_uniform_half(half) nounwind readonly alwaysinline {
%vec = insertelement <8 x half> poison, half %0, i32 0
%rcp = tail call <8 x half> @llvm.x86.avx512fp16.mask.rcp.sh(<8 x half> %vec, <8 x half> %vec, <8 x half> poison, i8 -1)
%ret = extractelement <8 x half> %rcp, i32 0
ret half %ret
}
declare <8 x half> @llvm.x86.avx512fp16.mask.rcp.ph.128(<8 x half>, <8 x half>, i8)
define <4 x half> @__rcp_varying_half(<4 x half>) nounwind readonly alwaysinline {
%vec = shufflevector <4 x half> %0, <4 x half> poison,
<8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 poison, i32 poison, i32 poison, i32 poison>
%rcp = tail call <8 x half> @llvm.x86.avx512fp16.mask.rcp.ph.128(<8 x half> %vec, <8 x half> poison, i8 -1)
%ret = shufflevector <8 x half> %rcp, <8 x half> poison,
<4 x i32> <i32 0, i32 1, i32 2, i32 3>
ret <4 x half> %ret
}
declare <8 x half> @llvm.x86.avx512fp16.mask.rsqrt.sh(<8 x half>, <8 x half>, <8 x half>, i8)
define half @__rsqrt_uniform_half(half) nounwind readnone alwaysinline {
%vec = insertelement <8 x half> poison, half %0, i32 0
%rsqrt = tail call <8 x half> @llvm.x86.avx512fp16.mask.rsqrt.sh(<8 x half> %vec, <8 x half> %vec, <8 x half> poison, i8 -1)
%ret = extractelement <8 x half> %rsqrt, i32 0
ret half %ret
}
declare <8 x half> @llvm.x86.avx512fp16.mask.rsqrt.ph.128(<8 x half>, <8 x half>, i8)
define <4 x half> @__rsqrt_varying_half(<4 x half>) nounwind readnone alwaysinline {
%vec = shufflevector <4 x half> %0, <4 x half> poison,
<8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 poison, i32 poison, i32 poison, i32 poison>
%rsqrt = tail call <8 x half> @llvm.x86.avx512fp16.mask.rsqrt.ph.128(<8 x half> %vec, <8 x half> poison, i8 -1)
%ret = shufflevector <8 x half> %rsqrt, <8 x half> poison,
<4 x i32> <i32 0, i32 1, i32 2, i32 3>
ret <4 x half> %ret
}