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Add avx512gnr* targets

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This commit is contained in:
Arina Neshlyaeva
2025-12-15 18:52:41 -08:00
committed by aneshlya
parent 7f1e1a3b79
commit b86e1770ce
45 changed files with 305 additions and 85 deletions
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.github/workflows/ispc-ci.yml
+2 -1
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@@ -41,7 +41,8 @@ env:
"avx2vnni-i32x4", "avx2vnni-i32x8", "avx2vnni-i32x16",
"avx512skx-x4", "avx512skx-x8", "avx512skx-x16", "avx512skx-x64", "avx512skx-x32",
"avx512icl-x4", "avx512icl-x8", "avx512icl-x16", "avx512icl-x64", "avx512icl-x32",
"avx512spr-x4", "avx512spr-x8", "avx512spr-x16", "avx512spr-x64", "avx512spr-x32"]'
"avx512spr-x4", "avx512spr-x8", "avx512spr-x16", "avx512spr-x64", "avx512spr-x32",
"avx512gnr-x4", "avx512gnr-x8", "avx512gnr-x16", "avx512gnr-x64", "avx512gnr-x32"]'
TARGETS_FULL_ARM: '["neon-i32x4", "neon-i32x8", "neon-i8x16", "neon-i16x8", "neon-i8x32", "neon-i16x16"]'
OPTSETS_FULL: "-O0 -O1 -O2"
ISPC_ANDROID_NDK_PATH: "/usr/local/share/android-ndk"
.github/workflows/linux-nightly-trunk.yml
+1
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@@ -38,6 +38,7 @@ jobs:
"avx512skx-x4", "avx512skx-x8", "avx512skx-x16", "avx512skx-x64", "avx512skx-x32",
"avx512icl-x4", "avx512icl-x8", "avx512icl-x16", "avx512icl-x64", "avx512icl-x32",
"avx512spr-x4", "avx512spr-x8", "avx512spr-x16", "avx512spr-x64", "avx512spr-x32",
"avx512gnr-x4", "avx512gnr-x8", "avx512gnr-x16", "avx512gnr-x64", "avx512gnr-x32",
"avx10.2dmr-x4", "avx10.2dmr-x8", "avx10.2dmr-x16", "avx10.2dmr-x64", "avx10.2dmr-x32"]
steps:
- run: echo "Defining targets"
.github/workflows/nightly-next.yml
+1
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@@ -35,6 +35,7 @@ jobs:
"avx512skx-x4", "avx512skx-x8", "avx512skx-x16", "avx512skx-x64", "avx512skx-x32",
"avx512icl-x4", "avx512icl-x8", "avx512icl-x16", "avx512icl-x64", "avx512icl-x32",
"avx512spr-x4", "avx512spr-x8", "avx512spr-x16", "avx512spr-x64", "avx512spr-x32",
"avx512gnr-x4", "avx512gnr-x8", "avx512gnr-x16", "avx512gnr-x64", "avx512gnr-x32",
"avx10.2dmr-x4", "avx10.2dmr-x8", "avx10.2dmr-x16", "avx10.2dmr-x64", "avx10.2dmr-x32"]
steps:
- run: echo "Defining targets"
CMakeLists.txt
+2 -1
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@@ -388,7 +388,8 @@ list(APPEND X86_TARGETS
avx512skx-x32 avx512skx-x64
avx512icl-x4 avx512icl-x8 avx512icl-x16 avx512icl-x16-nozmm
avx512icl-x32 avx512icl-x64
avx512spr-x4 avx512spr-x8 avx512spr-x16 avx512spr-x32 avx512spr-x64)
avx512spr-x4 avx512spr-x8 avx512spr-x16 avx512spr-x32 avx512spr-x64
avx512gnr-x4 avx512gnr-x8 avx512gnr-x16 avx512gnr-x32 avx512gnr-x64)
if (${LLVM_VERSION_NUMBER} VERSION_GREATER_EQUAL "20.1.2")
list(APPEND X86_TARGETS avx10_2dmr-x4 avx10_2dmr-x8 avx10_2dmr-x16 avx10_2dmr-x32 avx10_2dmr-x64)
builtins/target-avx512gnr-x16.ll
+6
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@@ -0,0 +1,6 @@
;; Copyright (c) 2025, Intel Corporation
;;
;; SPDX-License-Identifier: BSD-3-Clause
define(`WIDTH',`16')
define(`ISA',`AVX512SKX')
builtins/target-avx512gnr-x32.ll
+6
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@@ -0,0 +1,6 @@
;; Copyright (c) 2025, Intel Corporation
;;
;; SPDX-License-Identifier: BSD-3-Clause
define(`WIDTH',`32')
define(`ISA',`AVX512SKX')
builtins/target-avx512gnr-x4.ll
+6
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@@ -0,0 +1,6 @@
;; Copyright (c) 2025, Intel Corporation
;;
;; SPDX-License-Identifier: BSD-3-Clause
define(`WIDTH',`4')
define(`ISA',`AVX512SKX')
builtins/target-avx512gnr-x64.ll
+6
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@@ -0,0 +1,6 @@
;; Copyright (c) 2025, Intel Corporation
;;
;; SPDX-License-Identifier: BSD-3-Clause
define(`WIDTH',`64')
define(`ISA',`AVX512SKX')
builtins/target-avx512gnr-x8.ll
+6
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@@ -0,0 +1,6 @@
;; Copyright (c) 2025, Intel Corporation
;;
;; SPDX-License-Identifier: BSD-3-Clause
define(`WIDTH',`8')
define(`ISA',`AVX512SKX')
cmake/CommonStdlibBuiltins.cmake
+2 -2
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@@ -17,8 +17,8 @@ function(should_skip_target_for_os target os bit out_skip)
if ("${bit}" STREQUAL "32")
set(skip TRUE)
endif()
# ISPC doesn't support avx512spr targets on macOS
if ("${target}" MATCHES "avx512spr" OR "${target}" MATCHES "avx10")
# ISPC doesn't support avx512spr/avx512gnr targets on macOS
if ("${target}" MATCHES "avx512spr" OR "${target}" MATCHES "avx512gnr" OR "${target}" MATCHES "avx10")
set(skip TRUE)
endif()
endif()
cmake/StdlibFamilies.cmake
+5 -5
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@@ -53,11 +53,11 @@ function(define_stdlib_families)
# Note: nozmm targets are excluded - they produce different stdlib that avoids ZMM instructions
set(FAMILY_DEFINITIONS
# AVX512 families - use generic targets
"i1x4:generic-i1x4:avx512skx-x4,avx512icl-x4,avx512spr-x4${AVX10_X4}"
"i1x8:generic-i1x8:avx512skx-x8,avx512icl-x8,avx512spr-x8${AVX10_X8}"
"i1x16:generic-i1x16:avx512skx-x16,avx512icl-x16,avx512spr-x16${AVX10_X16}"
"i1x32:generic-i1x32:avx512skx-x32,avx512icl-x32,avx512spr-x32${AVX10_X32}"
"i1x64:generic-i1x64:avx512skx-x64,avx512icl-x64,avx512spr-x64${AVX10_X64}"
"i1x4:generic-i1x4:avx512skx-x4,avx512icl-x4,avx512spr-x4,avx512gnr-x4${AVX10_X4}"
"i1x8:generic-i1x8:avx512skx-x8,avx512icl-x8,avx512spr-x8,avx512gnr-x8${AVX10_X8}"
"i1x16:generic-i1x16:avx512skx-x16,avx512icl-x16,avx512spr-x16,avx512gnr-x16${AVX10_X16}"
"i1x32:generic-i1x32:avx512skx-x32,avx512icl-x32,avx512spr-x32,avx512gnr-x32${AVX10_X32}"
"i1x64:generic-i1x64:avx512skx-x64,avx512icl-x64,avx512spr-x64,avx512gnr-x64${AVX10_X64}"
# SSE/AVX families that match generic implementation
"i32x4:generic-i32x4:sse2-i32x4,sse4-i32x4"
contrib/ispc.vim
+1 -1
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@@ -31,7 +31,7 @@ syn keyword ispcDefine ISPC ISPC_POINTER_SIZE ISPC_MAJOR_VERSION ISPC_MINOR_VER
\ UINT8_MAX UINT16_MAX UINT32_MAX UINT64_MAX
\ F16_MIN FLT_MIN DBL_MIN F16_MAX FLT_MAX DBL_MAX
\ ISPC_TARGET_NEON ISPC_TARGET_SSE2 ISPC_TARGET_SSE4 ISPC_TARGET_AVX ISPC_TARGET_AVX2 ISPC_TARGET_AVX512KNL ISPC_TARGET_AVX512SKX
\ ISPC_TARGET_AVX512SPR ISPC_TARGET_AVX10_2DMR
\ ISPC_TARGET_AVX512SPR ISPC_TARGET_AVX512GNR ISPC_TARGET_AVX10_2DMR
\ ISPC_TARGET_XELP ISPC_TARGET_XEHPG ISPC_TARGET_XEHPC ISPC_TARGET_XELPG ISPC_TARGET_XE2HPG ISPC_TARGET_XE2LPG
docs/ispc.rst
+5 -3
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@@ -1255,7 +1255,8 @@ avx2 AVX2 Intel Haswell (2013) [#]_, AMD Excavator
avx2vnni AVX2 Intel Alder Lake (2021), AMD Zen5 (2024)
avx512skx AVX-512 Intel Skylake Xeon (2017), AMD Zen4 (2022)
avx512icl AVX-512 Intel Icelake (2019), AMD Zen4 (2022)
avx512spr AVX-512 Intel Sapphire Rapids (2023)
avx512spr AVX-512 + AMX Intel Sapphire Rapids (2023)
avx512gnr AVX-512 + AMX FP16 Intel Granite Rapids (2024)
avx10.2dmr AVX10.2 + AMX Intel Diamond Rapids (2026+)
neon ARMv8 NEON ARM Cortex-A35/A53/A57 (2012-2015)
============= ========================= ===========================================================
@@ -1336,7 +1337,8 @@ x86 targets:
``avx512skx-x4``, ``avx512skx-x8``, ``avx512skx-x16``, ``avx512skx-x32``,
``avx512skx-x64``, ``avx512icl-x4``, ``avx512icl-x8``, ``avx512icl-x16``, ``avx512icl-x32``,
``avx512icl-x64``, ``avx512spr-x4``, ``avx512spr-x8``, ``avx512spr-x16``, ``avx512spr-x32``,
``avx512spr-x64``.
``avx512spr-x64``, ``avx512gnr-x4``, ``avx512gnr-x8``, ``avx512gnr-x16``, ``avx512gnr-x32``,
``avx512gnr-x64``.
Neon targets:
@@ -1419,7 +1421,7 @@ preprocessor runs:
* - ISPC
- 1
- Enables detecting that the ``ispc`` compiler is processing the file
* - ISPC_TARGET_{NEON, SSE2, SSE4, AVX, AVX2, AVX512SKX, AVX512ICL, AVX512SPR, AVX10_2}
* - ISPC_TARGET_{NEON, SSE2, SSE4, AVX, AVX2, AVX512SKX, AVX512ICL, AVX512SPR, AVX512GNR, AVX10_2DMR}
- 1
- One of these will be set, depending on the compilation target
* - ISPC_POINTER_SIZE
examples/cpu/amx/CMakeLists.txt
+2 -2
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@@ -100,8 +100,8 @@ message(STATUS "AMX support detected via: ${AMX_DETECTION_METHOD}")
if(AMX_SUPPORTED)
set (ISPC_SRC_NAME "amx_matmul")
set (TARGET_SOURCES ${CMAKE_CURRENT_SOURCE_DIR}/amx_matmul.cpp)
set (ISPC_FLAGS -O2 --target=avx512spr-x32 --cpu=gnr --enable-llvm-intrinsics --pic)
set (ISPC_IA_TARGETS "avx512spr-x32")
set (ISPC_FLAGS -O2 --target=avx512gnr-x32 --enable-llvm-intrinsics --pic)
set (ISPC_IA_TARGETS "avx512gnr-x32")
add_ispc_example(NAME "amx"
ISPC_IA_TARGETS ${ISPC_IA_TARGETS}
scripts/alloy.py
+3 -1
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@@ -403,8 +403,10 @@ def check_targets():
["SSE2", "SSE4.1", "SSE4.2", "AVX", "AVX1.1", "AVX2", "AVX2VNNI", "SKX", "ICL"], "-icl", False]),
("SPR", [["avx512spr-x16", "avx512spr-x8", "avx512spr-x4", "avx512spr-x64", "avx512spr-x32"],
["SSE2", "SSE4.1", "SSE4.2", "AVX", "AVX1.1", "AVX2", "AVX2VNNI", "SKX", "ICL", "SPR"], "-spr", False]),
("GNR", [["avx512gnr-x16", "avx512gnr-x8", "avx512gnr-x4", "avx512gnr-x64", "avx512gnr-x32"],
["SSE2", "SSE4.1", "SSE4.2", "AVX", "AVX1.1", "AVX2", "AVX2VNNI", "SKX", "ICL", "SPR", "GNR"], "-gnr", False]),
("DMR", [["avx10.2dmr-x16", "avx10.2dmr-x8", "avx10.2dmr-x4", "avx10.2dmr-x64", "avx10.2dmr-x32"],
["SSE2", "SSE4.1", "SSE4.2", "AVX", "AVX1.1", "AVX2", "AVX2VNNI", "SKX", "ICL", "SPR", "DMR"], "-dmr", False])
["SSE2", "SSE4.1", "SSE4.2", "AVX", "AVX1.1", "AVX2", "AVX2VNNI", "SKX", "ICL", "SPR", "GNR", "DMR"], "-dmr", False])
])
hw_arch = take_lines(check_isa, "first").split()[1]
scripts/dump_stdlib_deps.py
+10 -5
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@@ -164,29 +164,34 @@ class ISPCTarget:
'neon-i32x8': 'generic-i32x8',
# AVX10.2 targets
'avx10.2dmr-x4': 'avx512spr-x4',
'avx10.2dmr-x8': 'avx512spr-x8',
'avx10.2dmr-x16': 'avx512spr-x16',
'avx10.2dmr-x32': 'avx512spr-x32',
'avx10.2dmr-x64': 'avx512spr-x64',
'avx10.2dmr-x4': 'avx512gnr-x4',
'avx10.2dmr-x8': 'avx512gnr-x8',
'avx10.2dmr-x16': 'avx512gnr-x16',
'avx10.2dmr-x32': 'avx512gnr-x32',
'avx10.2dmr-x64': 'avx512gnr-x64',
# AVX512 hierarchy
'avx512gnr-x4': 'avx512spr-x4',
'avx512spr-x4': 'avx512icl-x4',
'avx512icl-x4': 'avx512skx-x4',
'avx512skx-x4': 'generic-i1x4',
'avx512gnr-x8': 'avx512spr-x8',
'avx512spr-x8': 'avx512icl-x8',
'avx512icl-x8': 'avx512skx-x8',
'avx512skx-x8': 'generic-i1x8',
'avx512gnr-x16': 'avx512spr-x16',
'avx512spr-x16': 'avx512icl-x16',
'avx512icl-x16': 'avx512skx-x16',
'avx512skx-x16': 'generic-i1x16',
'avx512gnr-x32': 'avx512spr-x32',
'avx512spr-x32': 'avx512icl-x32',
'avx512icl-x32': 'avx512skx-x32',
'avx512skx-x32': 'generic-i1x32',
'avx512gnr-x64': 'avx512spr-x64',
'avx512spr-x64': 'avx512icl-x64',
'avx512icl-x64': 'avx512skx-x64',
'avx512skx-x64': 'generic-i1x64',
src/builtins.cpp
+10 -5
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@@ -480,21 +480,24 @@ std::unordered_map<ISPCTarget, ISPCTarget> targetParentMap = {
{ISPCTarget::rvv_x4, ISPCTarget::generic_i1x4},
#if ISPC_LLVM_VERSION >= ISPC_LLVM_20_0
{ISPCTarget::avx10_2dmr_x4, ISPCTarget::avx512spr_x4},
{ISPCTarget::avx10_2dmr_x8, ISPCTarget::avx512spr_x8},
{ISPCTarget::avx10_2dmr_x16, ISPCTarget::avx512spr_x16},
{ISPCTarget::avx10_2dmr_x32, ISPCTarget::avx512spr_x32},
{ISPCTarget::avx10_2dmr_x64, ISPCTarget::avx512spr_x64},
{ISPCTarget::avx10_2dmr_x4, ISPCTarget::avx512gnr_x4},
{ISPCTarget::avx10_2dmr_x8, ISPCTarget::avx512gnr_x8},
{ISPCTarget::avx10_2dmr_x16, ISPCTarget::avx512gnr_x16},
{ISPCTarget::avx10_2dmr_x32, ISPCTarget::avx512gnr_x32},
{ISPCTarget::avx10_2dmr_x64, ISPCTarget::avx512gnr_x64},
#endif
{ISPCTarget::avx512gnr_x4, ISPCTarget::avx512spr_x4},
{ISPCTarget::avx512spr_x4, ISPCTarget::avx512icl_x4},
{ISPCTarget::avx512icl_x4, ISPCTarget::avx512skx_x4},
{ISPCTarget::avx512skx_x4, ISPCTarget::generic_i1x4},
{ISPCTarget::avx512gnr_x8, ISPCTarget::avx512spr_x8},
{ISPCTarget::avx512spr_x8, ISPCTarget::avx512icl_x8},
{ISPCTarget::avx512icl_x8, ISPCTarget::avx512skx_x8},
{ISPCTarget::avx512skx_x8, ISPCTarget::generic_i1x8},
{ISPCTarget::avx512gnr_x16, ISPCTarget::avx512spr_x16},
{ISPCTarget::avx512spr_x16, ISPCTarget::avx512icl_x16},
{ISPCTarget::avx512icl_x16, ISPCTarget::avx512skx_x16},
{ISPCTarget::avx512skx_x16, ISPCTarget::generic_i1x16},
@@ -502,10 +505,12 @@ std::unordered_map<ISPCTarget, ISPCTarget> targetParentMap = {
{ISPCTarget::avx512icl_x16_nozmm, ISPCTarget::avx512skx_x16_nozmm},
{ISPCTarget::avx512skx_x16_nozmm, ISPCTarget::generic_i1x16},
{ISPCTarget::avx512gnr_x32, ISPCTarget::avx512spr_x32},
{ISPCTarget::avx512spr_x32, ISPCTarget::avx512icl_x32},
{ISPCTarget::avx512icl_x32, ISPCTarget::avx512skx_x32},
{ISPCTarget::avx512skx_x32, ISPCTarget::generic_i1x32},
{ISPCTarget::avx512gnr_x64, ISPCTarget::avx512spr_x64},
{ISPCTarget::avx512spr_x64, ISPCTarget::avx512icl_x64},
{ISPCTarget::avx512icl_x64, ISPCTarget::avx512skx_x64},
{ISPCTarget::avx512skx_x64, ISPCTarget::generic_i1x64},
src/isa.h
+6 -3
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@@ -21,7 +21,8 @@ enum ISA {
SKX_AVX512 = 8,
ICL_AVX512 = 9,
SPR_AVX512 = 10,
DMR_AVX10_2 = 11,
GNR_AVX512 = 11,
DMR_AVX10_2 = 12,
COUNT
};
@@ -195,7 +196,7 @@ UNUSED_ATTR static enum ISA get_x86_isa() {
UNUSED_ATTR int tgl = icl && avx512_vp2intersect;
int spr =
icl && avx512_bf16 && avx512_amx_bf16 && avx512_amx_tile && avx512_amx_int8 && avx_vnni && avx512_fp16;
UNUSED_ATTR int gnr = spr && amxfp16 && prefetchi;
int gnr = spr && amxfp16 && prefetchi;
int avx10 = (info3[3] & (1 << 19)) != 0;
@@ -220,7 +221,9 @@ UNUSED_ATTR static enum ISA get_x86_isa() {
return DMR_AVX10_2;
}
}
if (spr) {
if (gnr) {
return GNR_AVX512;
} else if (spr) {
return SPR_AVX512;
} else if (icl) {
return ICL_AVX512;
src/ispc.cpp
+34 -13
View File
@@ -251,12 +251,14 @@ static ISPCTarget lGetSystemISA() {
return ISPCTarget::avx512icl_x16;
case Target::ISA::SPR_AVX512:
return ISPCTarget::avx512spr_x16;
case Target::ISA::GNR_AVX512:
return ISPCTarget::avx512gnr_x16;
case Target::ISA::DMR_AVX10_2:
// Return SPR target for LLVM versions < 20.0
#if ISPC_LLVM_VERSION >= ISPC_LLVM_20_0
return ISPCTarget::avx10_2dmr_x16;
#else
return ISPCTarget::avx512spr_x16;
return ISPCTarget::avx512gnr_x16;
#endif
default:
Error(SourcePos(), "Detected unsupported x86 ISA. Exiting.");
@@ -1028,10 +1030,13 @@ Target::Target(Arch arch, const char *cpu, ISPCTarget ispc_target, PICLevel picL
#endif
case CPU_SPR:
case CPU_GNR:
m_ispc_target = ISPCTarget::avx512spr_x16;
break;
case CPU_GNR:
m_ispc_target = ISPCTarget::avx512gnr_x16;
break;
case CPU_ZNVER4:
#if ISPC_LLVM_VERSION >= ISPC_LLVM_20_0
case CPU_ZNVER5:
@@ -1577,7 +1582,8 @@ Target::Target(Arch arch, const char *cpu, ISPCTarget ispc_target, PICLevel picL
CPUfromISA = (m_ispc_target == ISPCTarget::avx512icl_x32) ? CPU_ICL : CPU_SKX;
break;
case ISPCTarget::avx512spr_x4:
this->m_isa = Target::SPR_AVX512;
case ISPCTarget::avx512gnr_x4:
this->m_isa = (m_ispc_target == ISPCTarget::avx512gnr_x4) ? Target::GNR_AVX512 : Target::SPR_AVX512;
this->m_nativeVectorWidth = 16;
this->m_nativeVectorAlignment = 64;
this->m_dataTypeWidth = 32;
@@ -1589,12 +1595,13 @@ Target::Target(Arch arch, const char *cpu, ISPCTarget ispc_target, PICLevel picL
setCapabilities({TargetCapability::HalfConverts, TargetCapability::HalfFullSupport, TargetCapability::Rand,
TargetCapability::Rsqrtd, TargetCapability::Rcpd, TargetCapability::Fp16Support,
TargetCapability::IntelVNNI, TargetCapability::ConflictDetection});
CPUfromISA = CPU_SPR;
CPUfromISA = (m_ispc_target == ISPCTarget::avx512gnr_x4) ? CPU_GNR : CPU_SPR;
this->m_funcAttributes.push_back(std::make_pair("prefer-vector-width", "256"));
this->m_funcAttributes.push_back(std::make_pair("min-legal-vector-width", "256"));
break;
case ISPCTarget::avx512spr_x8:
this->m_isa = Target::SPR_AVX512;
case ISPCTarget::avx512gnr_x8:
this->m_isa = (m_ispc_target == ISPCTarget::avx512gnr_x8) ? Target::GNR_AVX512 : Target::SPR_AVX512;
this->m_nativeVectorWidth = 16;
this->m_nativeVectorAlignment = 64;
this->m_dataTypeWidth = 32;
@@ -1606,12 +1613,13 @@ Target::Target(Arch arch, const char *cpu, ISPCTarget ispc_target, PICLevel picL
setCapabilities({TargetCapability::HalfConverts, TargetCapability::HalfFullSupport, TargetCapability::Rand,
TargetCapability::Rsqrtd, TargetCapability::Rcpd, TargetCapability::Fp16Support,
TargetCapability::IntelVNNI, TargetCapability::ConflictDetection});
CPUfromISA = CPU_SPR;
CPUfromISA = (m_ispc_target == ISPCTarget::avx512gnr_x8) ? CPU_GNR : CPU_SPR;
this->m_funcAttributes.push_back(std::make_pair("prefer-vector-width", "256"));
this->m_funcAttributes.push_back(std::make_pair("min-legal-vector-width", "256"));
break;
case ISPCTarget::avx512spr_x16:
this->m_isa = Target::SPR_AVX512;
case ISPCTarget::avx512gnr_x16:
this->m_isa = (m_ispc_target == ISPCTarget::avx512gnr_x16) ? Target::GNR_AVX512 : Target::SPR_AVX512;
this->m_nativeVectorWidth = 16;
this->m_nativeVectorAlignment = 64;
this->m_dataTypeWidth = 32;
@@ -1623,12 +1631,13 @@ Target::Target(Arch arch, const char *cpu, ISPCTarget ispc_target, PICLevel picL
setCapabilities({TargetCapability::HalfConverts, TargetCapability::HalfFullSupport, TargetCapability::Rand,
TargetCapability::Rsqrtd, TargetCapability::Rcpd, TargetCapability::Fp16Support,
TargetCapability::IntelVNNI, TargetCapability::ConflictDetection});
CPUfromISA = CPU_SPR;
CPUfromISA = (m_ispc_target == ISPCTarget::avx512gnr_x16) ? CPU_GNR : CPU_SPR;
this->m_funcAttributes.push_back(std::make_pair("prefer-vector-width", "512"));
this->m_funcAttributes.push_back(std::make_pair("min-legal-vector-width", "512"));
break;
case ISPCTarget::avx512spr_x64:
this->m_isa = Target::SPR_AVX512;
case ISPCTarget::avx512gnr_x64:
this->m_isa = (m_ispc_target == ISPCTarget::avx512gnr_x64) ? Target::GNR_AVX512 : Target::SPR_AVX512;
this->m_nativeVectorWidth = 64;
this->m_nativeVectorAlignment = 64;
this->m_dataTypeWidth = 8;
@@ -1640,10 +1649,11 @@ Target::Target(Arch arch, const char *cpu, ISPCTarget ispc_target, PICLevel picL
setCapabilities({TargetCapability::HalfConverts, TargetCapability::HalfFullSupport, TargetCapability::Rand,
TargetCapability::Fp16Support, TargetCapability::IntelVNNI,
TargetCapability::ConflictDetection});
CPUfromISA = CPU_SPR;
CPUfromISA = (m_ispc_target == ISPCTarget::avx512gnr_x64) ? CPU_GNR : CPU_SPR;
break;
case ISPCTarget::avx512spr_x32:
this->m_isa = Target::SPR_AVX512;
case ISPCTarget::avx512gnr_x32:
this->m_isa = (m_ispc_target == ISPCTarget::avx512gnr_x32) ? Target::GNR_AVX512 : Target::SPR_AVX512;
this->m_nativeVectorWidth = 64;
this->m_nativeVectorAlignment = 64;
this->m_dataTypeWidth = 16;
@@ -1655,7 +1665,7 @@ Target::Target(Arch arch, const char *cpu, ISPCTarget ispc_target, PICLevel picL
setCapabilities({TargetCapability::HalfConverts, TargetCapability::HalfFullSupport, TargetCapability::Rand,
TargetCapability::Fp16Support, TargetCapability::IntelVNNI,
TargetCapability::ConflictDetection});
CPUfromISA = CPU_SPR;
CPUfromISA = (m_ispc_target == ISPCTarget::avx512gnr_x32) ? CPU_GNR : CPU_SPR;
break;
#if ISPC_LLVM_VERSION >= ISPC_LLVM_20_0
case ISPCTarget::avx10_2dmr_x4:
@@ -2086,6 +2096,7 @@ Target::Target(Arch arch, const char *cpu, ISPCTarget ispc_target, PICLevel picL
case Target::SKX_AVX512:
case Target::ICL_AVX512:
case Target::SPR_AVX512:
case Target::GNR_AVX512:
this->setWarning(PerfWarningType::DIVModInt);
break;
// TODO: Add warnings for AVX10
@@ -2127,7 +2138,7 @@ Target::Target(Arch arch, const char *cpu, ISPCTarget ispc_target, PICLevel picL
if ((m_ispc_target == ISPCTarget::generic_i32x16 || m_ispc_target == ISPCTarget::generic_i1x16 ||
m_ispc_target == ISPCTarget::generic_i1x32 || m_ispc_target == ISPCTarget::generic_i1x64) &&
(CPUID == CPU_SKX || CPUID == CPU_ICL || CPUID == CPU_SPR
(CPUID == CPU_SKX || CPUID == CPU_ICL || CPUID == CPU_SPR || CPUID == CPU_GNR
#if LLVM_VERSION >= ISPC_LLVM_20_0
|| CPUID == CPU_DMR
#endif
@@ -2672,6 +2683,8 @@ const char *Target::ISAToString(ISA isa) {
return "avx512icl";
case Target::SPR_AVX512:
return "avx512spr";
case Target::GNR_AVX512:
return "avx512gnr";
#if ISPC_LLVM_VERSION >= ISPC_LLVM_20_0
case Target::DMR_AVX10_2:
return "avx10.2dmr";
@@ -2741,6 +2754,8 @@ const char *Target::ISAToTargetString(ISA isa) {
return "avx512icl-x16";
case Target::SPR_AVX512:
return "avx512spr-x16";
case Target::GNR_AVX512:
return "avx512gnr-x16";
#if ISPC_LLVM_VERSION >= ISPC_LLVM_20_0
case Target::DMR_AVX10_2:
return "avx10.2dmr-x16";
@@ -2804,6 +2819,12 @@ Target::ISA Target::TargetToISA(ISPCTarget target) {
case ISPCTarget::avx512spr_x32:
case ISPCTarget::avx512spr_x64:
return Target::ISA::SPR_AVX512;
case ISPCTarget::avx512gnr_x4:
case ISPCTarget::avx512gnr_x8:
case ISPCTarget::avx512gnr_x16:
case ISPCTarget::avx512gnr_x32:
case ISPCTarget::avx512gnr_x64:
return Target::ISA::GNR_AVX512;
case ISPCTarget::avx10_2dmr_x4:
case ISPCTarget::avx10_2dmr_x8:
case ISPCTarget::avx10_2dmr_x16:
src/ispc.h
+1
View File
@@ -255,6 +255,7 @@ class Target {
SKX_AVX512 = dispatch::ISA::SKX_AVX512,
ICL_AVX512 = dispatch::ISA::ICL_AVX512,
SPR_AVX512 = dispatch::ISA::SPR_AVX512,
GNR_AVX512 = dispatch::ISA::GNR_AVX512,
DMR_AVX10_2 = dispatch::ISA::DMR_AVX10_2,
#ifdef ISPC_ARM_ENABLED
NEON,
src/target_enums.cpp
+41 -1
View File
@@ -188,9 +188,24 @@ ISPCTarget operator++(ISPCTarget &target, int dummy) {
static_assert(static_cast<underlying>(ISPCTarget::avx512spr_x64) ==
static_cast<underlying>(ISPCTarget::avx512spr_x32) + 1,
"Enum ISPCTarget is not sequential");
static_assert(static_cast<underlying>(ISPCTarget::avx10_2dmr_x4) ==
static_assert(static_cast<underlying>(ISPCTarget::avx512gnr_x4) ==
static_cast<underlying>(ISPCTarget::avx512spr_x64) + 1,
"Enum ISPCTarget is not sequential");
static_assert(static_cast<underlying>(ISPCTarget::avx512gnr_x8) ==
static_cast<underlying>(ISPCTarget::avx512gnr_x4) + 1,
"Enum ISPCTarget is not sequential");
static_assert(static_cast<underlying>(ISPCTarget::avx512gnr_x16) ==
static_cast<underlying>(ISPCTarget::avx512gnr_x8) + 1,
"Enum ISPCTarget is not sequential");
static_assert(static_cast<underlying>(ISPCTarget::avx512gnr_x32) ==
static_cast<underlying>(ISPCTarget::avx512gnr_x16) + 1,
"Enum ISPCTarget is not sequential");
static_assert(static_cast<underlying>(ISPCTarget::avx512gnr_x64) ==
static_cast<underlying>(ISPCTarget::avx512gnr_x32) + 1,
"Enum ISPCTarget is not sequential");
static_assert(static_cast<underlying>(ISPCTarget::avx10_2dmr_x4) ==
static_cast<underlying>(ISPCTarget::avx512gnr_x64) + 1,
"Enum ISPCTarget is not sequential");
static_assert(static_cast<underlying>(ISPCTarget::avx10_2dmr_x8) ==
static_cast<underlying>(ISPCTarget::avx10_2dmr_x4) + 1,
"Enum ISPCTarget is not sequential");
@@ -434,6 +449,16 @@ ISPCTarget ParseISPCTarget(std::string target) {
return ISPCTarget::avx512spr_x32;
} else if (target == "avx512spr-x64") {
return ISPCTarget::avx512spr_x64;
} else if (target == "avx512gnr-x4") {
return ISPCTarget::avx512gnr_x4;
} else if (target == "avx512gnr-x8") {
return ISPCTarget::avx512gnr_x8;
} else if (target == "avx512gnr-x16") {
return ISPCTarget::avx512gnr_x16;
} else if (target == "avx512gnr-x32") {
return ISPCTarget::avx512gnr_x32;
} else if (target == "avx512gnr-x64") {
return ISPCTarget::avx512gnr_x64;
#if ISPC_LLVM_VERSION >= ISPC_LLVM_20_0
} else if (target == "avx10.2dmr-x4") {
return ISPCTarget::avx10_2dmr_x4;
@@ -629,6 +654,16 @@ std::string ISPCTargetToString(ISPCTarget target) {
return "avx512spr-x32";
case ISPCTarget::avx512spr_x64:
return "avx512spr-x64";
case ISPCTarget::avx512gnr_x4:
return "avx512gnr-x4";
case ISPCTarget::avx512gnr_x8:
return "avx512gnr-x8";
case ISPCTarget::avx512gnr_x16:
return "avx512gnr-x16";
case ISPCTarget::avx512gnr_x32:
return "avx512gnr-x32";
case ISPCTarget::avx512gnr_x64:
return "avx512gnr-x64";
case ISPCTarget::avx10_2dmr_x4:
return "avx10.2dmr-x4";
case ISPCTarget::avx10_2dmr_x8:
@@ -757,6 +792,11 @@ bool ISPCTargetIsX86(ISPCTarget target) {
case ISPCTarget::avx512spr_x16:
case ISPCTarget::avx512spr_x32:
case ISPCTarget::avx512spr_x64:
case ISPCTarget::avx512gnr_x4:
case ISPCTarget::avx512gnr_x8:
case ISPCTarget::avx512gnr_x16:
case ISPCTarget::avx512gnr_x32:
case ISPCTarget::avx512gnr_x64:
case ISPCTarget::avx10_2dmr_x4:
case ISPCTarget::avx10_2dmr_x8:
case ISPCTarget::avx10_2dmr_x16:
src/target_enums.h
+5
View File
@@ -75,6 +75,11 @@ enum class ISPCTarget {
avx512spr_x16,
avx512spr_x32,
avx512spr_x64,
avx512gnr_x4,
avx512gnr_x8,
avx512gnr_x16,
avx512gnr_x32,
avx512gnr_x64,
avx10_2dmr_x4,
avx10_2dmr_x8,
avx10_2dmr_x16,
src/target_registry.cpp
+7 -4
View File
@@ -171,13 +171,16 @@ static ISPCTarget lGetAliasTarget(ISPCTarget target) {
// Otherwise returns the canonicalized target
static ISPCTarget lCanonicalizeTarget(ISPCTarget target, TargetOS os, bool applyAliases) {
// Check if target is unsupported on this OS
// There's no Mac that supports SPR, so the decision is not support these targets when targeting macOS.
// There's no Mac that supports SPR/GNR, so the decision is not support these targets when targeting macOS.
// If these targets are linked in, then we still can use them for cross compilation, for example for Linux.
if (os == TargetOS::macos && (target == ISPCTarget::avx512spr_x4 || target == ISPCTarget::avx512spr_x8 ||
target == ISPCTarget::avx512spr_x16 || target == ISPCTarget::avx512spr_x32 ||
target == ISPCTarget::avx512spr_x64 || target == ISPCTarget::avx10_2dmr_x4 ||
target == ISPCTarget::avx10_2dmr_x8 || target == ISPCTarget::avx10_2dmr_x16 ||
target == ISPCTarget::avx10_2dmr_x32 || target == ISPCTarget::avx10_2dmr_x64)) {
target == ISPCTarget::avx512spr_x64 || target == ISPCTarget::avx512gnr_x4 ||
target == ISPCTarget::avx512gnr_x8 || target == ISPCTarget::avx512gnr_x16 ||
target == ISPCTarget::avx512gnr_x32 || target == ISPCTarget::avx512gnr_x64 ||
target == ISPCTarget::avx10_2dmr_x4 || target == ISPCTarget::avx10_2dmr_x8 ||
target == ISPCTarget::avx10_2dmr_x16 || target == ISPCTarget::avx10_2dmr_x32 ||
target == ISPCTarget::avx10_2dmr_x64)) {
return ISPCTarget::none;
}
stdlib/include/core.isph
+2 -2
View File
@@ -171,7 +171,7 @@ static const int32 programIndex = {ISPC_PROGRAM_INDEX_INITIALIZER};
#endif
#if defined(ISPC_TARGET_AVX512SKX) || defined(ISPC_TARGET_AVX512ICL) || defined(ISPC_TARGET_AVX512SPR) || \
defined(ISPC_TARGET_AVX10_2DMR)
defined(ISPC_TARGET_AVX512GNR) || defined(ISPC_TARGET_AVX10_2DMR)
#define ISPC_TARGET_HAS_ROTATE_VIA_SHUFFLE_8_VAL 1
#define ISPC_TARGET_HAS_ROTATE_VIA_SHUFFLE_16_VAL 1
#if TARGET_WIDTH <= 32
@@ -192,7 +192,7 @@ static const int32 programIndex = {ISPC_PROGRAM_INDEX_INITIALIZER};
#endif
#if defined(ISPC_TARGET_AVX512SKX) || defined(ISPC_TARGET_AVX512ICL) || defined(ISPC_TARGET_AVX512SPR) || \
defined(ISPC_TARGET_AVX10_2DMR)
defined(ISPC_TARGET_AVX512GNR) || defined(ISPC_TARGET_AVX10_2DMR)
#define ISPC_TARGET_HAS_SHIFT_VIA_SHUFFLE_8_VAL 1
#define ISPC_TARGET_HAS_SHIFT_VIA_SHUFFLE_16_VAL 1
#if TARGET_WIDTH < 64
tests/lit-tests/2770-1.ispc
+5
View File
@@ -3,17 +3,22 @@
// RUN: %{ispc} --target=avx512skx-x4 --nowrap -O2 --emit-asm --x86-asm-syntax=intel %s -o - | FileCheck %s --check-prefixes=CHECK_ALL,CHECK_SKX_INT8,CHECK_INT16,CHECK_INT32,CHECK_FLOAT,CHECK_DOUBLE,CHECK_INT64
// RUN: %{ispc} --target=avx512icl-x4 --nowrap -O2 --emit-asm --x86-asm-syntax=intel %s -o - | FileCheck %s --check-prefixes=CHECK_ALL,CHECK_SKX_INT8,CHECK_INT16,CHECK_INT32,CHECK_FLOAT,CHECK_DOUBLE,CHECK_INT64
// RUN: %{ispc} --target=avx512spr-x4 --nowrap -O2 --emit-asm --x86-asm-syntax=intel %s -o - | FileCheck %s --check-prefixes=CHECK_ALL,CHECK_SKX_INT8,CHECK_INT16,CHECK_INT32,CHECK_FLOAT,CHECK_DOUBLE,CHECK_INT64
// RUN: %{ispc} --target=avx512gnr-x4 --nowrap -O2 --emit-asm --x86-asm-syntax=intel %s -o - | FileCheck %s --check-prefixes=CHECK_ALL,CHECK_SKX_INT8,CHECK_INT16,CHECK_INT32,CHECK_FLOAT,CHECK_DOUBLE,CHECK_INT64
// RUN: %{ispc} --target=avx512skx-x8 --nowrap -O2 --emit-asm --x86-asm-syntax=intel %s -o - | FileCheck %s --check-prefixes=CHECK_ALL,CHECK_SKX_INT8,CHECK_INT16,CHECK_INT32,CHECK_FLOAT
// RUN: %{ispc} --target=avx512icl-x8 --nowrap -O2 --emit-asm --x86-asm-syntax=intel %s -o - | FileCheck %s --check-prefixes=CHECK_ALL,CHECK_SKX_INT8,CHECK_INT16,CHECK_INT32,CHECK_FLOAT
// RUN: %{ispc} --target=avx512spr-x8 --nowrap -O2 --emit-asm --x86-asm-syntax=intel %s -o - | FileCheck %s --check-prefixes=CHECK_ALL,CHECK_SKX_INT8,CHECK_INT16,CHECK_INT32,CHECK_FLOAT
// RUN: %{ispc} --target=avx512gnr-x8 --nowrap -O2 --emit-asm --x86-asm-syntax=intel %s -o - | FileCheck %s --check-prefixes=CHECK_ALL,CHECK_SKX_INT8,CHECK_INT16,CHECK_INT32,CHECK_FLOAT
// RUN: %{ispc} --target=avx512skx-x16 --nowrap -O2 --emit-asm --x86-asm-syntax=intel %s -o - | FileCheck %s --check-prefixes=CHECK_ALL,CHECK_INT8,CHECK_INT16,CHECK_INT32,CHECK_FLOAT
// RUN: %{ispc} --target=avx512icl-x16 --nowrap -O2 --emit-asm --x86-asm-syntax=intel %s -o - | FileCheck %s --check-prefixes=CHECK_ALL,CHECK_INT8,CHECK_INT16,CHECK_INT32,CHECK_FLOAT
// RUN: %{ispc} --target=avx512spr-x16 --nowrap -O2 --emit-asm --x86-asm-syntax=intel %s -o - | FileCheck %s --check-prefixes=CHECK_ALL,CHECK_INT8,CHECK_INT16,CHECK_INT32,CHECK_FLOAT
// RUN: %{ispc} --target=avx512gnr-x16 --nowrap -O2 --emit-asm --x86-asm-syntax=intel %s -o - | FileCheck %s --check-prefixes=CHECK_ALL,CHECK_INT8,CHECK_INT16,CHECK_INT32,CHECK_FLOAT
// RUN: %{ispc} --target=avx512skx-x32 --nowrap -O2 --emit-asm --x86-asm-syntax=intel %s -o - | FileCheck %s --check-prefixes=CHECK_ALL,CHECK_INT8
// RUN: %{ispc} --target=avx512icl-x32 --nowrap -O2 --emit-asm --x86-asm-syntax=intel %s -o - | FileCheck %s --check-prefixes=CHECK_ALL,CHECK_INT8
// RUN: %{ispc} --target=avx512spr-x32 --nowrap -O2 --emit-asm --x86-asm-syntax=intel %s -o - | FileCheck %s --check-prefixes=CHECK_ALL,CHECK_INT8
// RUN: %{ispc} --target=avx512gnr-x32 --nowrap -O2 --emit-asm --x86-asm-syntax=intel %s -o - | FileCheck %s --check-prefixes=CHECK_ALL,CHECK_INT8
// RUN: %{ispc} --target=avx512icl-x64 --nowrap -O2 --emit-asm --x86-asm-syntax=intel %s -o - | FileCheck %s --check-prefixes=CHECK_ALL,CHECK_INT8
// RUN: %{ispc} --target=avx512spr-x64 --nowrap -O2 --emit-asm --x86-asm-syntax=intel %s -o - | FileCheck %s --check-prefixes=CHECK_ALL,CHECK_INT8
// RUN: %{ispc} --target=avx512gnr-x64 --nowrap -O2 --emit-asm --x86-asm-syntax=intel %s -o - | FileCheck %s --check-prefixes=CHECK_ALL,CHECK_INT8
// REQUIRES: X86_ENABLED && !MACOS_HOST
tests/lit-tests/2832.ispc
+3 -4
View File
@@ -6,18 +6,17 @@
// RUN: %{ispc} --target=avx512icl-x4 --nowrap -O2 --emit-asm --x86-asm-syntax=intel %s -o - | FileCheck %s --check-prefixes=CHECK_ALL,CHECK_INT32,CHECK_FLOAT,CHECK_INT64,CHECK_DOUBLE
// RUN: %{ispc} --target=avx512skx-x4 --nowrap -O2 --emit-asm --x86-asm-syntax=intel %s -o - | FileCheck %s --check-prefixes=CHECK_ALL,CHECK_INT32,CHECK_FLOAT,CHECK_INT64,CHECK_DOUBLE
// RUN: %{ispc} --target=avx512spr-x4 --nowrap -O2 --emit-asm --x86-asm-syntax=intel %s -o - | FileCheck %s --check-prefixes=CHECK_ALL,CHECK_INT32,CHECK_FLOAT,CHECK_INT64,CHECK_DOUBLE
// RUN: %{ispc} --target=avx512gnr-x4 --nowrap -O2 --emit-asm --x86-asm-syntax=intel %s -o - | FileCheck %s --check-prefixes=CHECK_ALL,CHECK_INT32,CHECK_FLOAT,CHECK_INT64,CHECK_DOUBLE
// RUN: %{ispc} --target=avx512icl-x8 --nowrap -O2 --emit-asm --x86-asm-syntax=intel %s -o - | FileCheck %s --check-prefixes=CHECK_ALL,CHECK_INT16,CHECK_INT32,CHECK_FLOAT
// RUN: %{ispc} --target=avx512skx-x8 --nowrap -O2 --emit-asm --x86-asm-syntax=intel %s -o - | FileCheck %s --check-prefixes=CHECK_ALL,CHECK_INT16,CHECK_INT32,CHECK_FLOAT
// RUN: %{ispc} --target=avx512spr-x8 --nowrap -O2 --emit-asm --x86-asm-syntax=intel %s -o - | FileCheck %s --check-prefixes=CHECK_ALL,CHECK_INT16,CHECK_INT32,CHECK_FLOAT
// RUN: %{ispc} --target=avx512icl-x8 --nowrap -O2 --emit-asm --x86-asm-syntax=intel %s -o - | FileCheck %s --check-prefixes=CHECK_ALL,CHECK_INT16,CHECK_INT32,CHECK_FLOAT
// RUN: %{ispc} --target=avx512skx-x8 --nowrap -O2 --emit-asm --x86-asm-syntax=intel %s -o - | FileCheck %s --check-prefixes=CHECK_ALL,CHECK_INT16,CHECK_INT32,CHECK_FLOAT
// RUN: %{ispc} --target=avx512spr-x8 --nowrap -O2 --emit-asm --x86-asm-syntax=intel %s -o - | FileCheck %s --check-prefixes=CHECK_ALL,CHECK_INT16,CHECK_INT32,CHECK_FLOAT
// RUN: %{ispc} --target=avx512gnr-x8 --nowrap -O2 --emit-asm --x86-asm-syntax=intel %s -o - | FileCheck %s --check-prefixes=CHECK_ALL,CHECK_INT16,CHECK_INT32,CHECK_FLOAT
// RUN: %{ispc} --target=avx512icl-x16 --nowrap -O2 --emit-asm --x86-asm-syntax=intel %s -o - | FileCheck %s --check-prefixes=CHECK_ALL,CHECK_INT8,CHECK_INT16,CHECK_INT32,CHECK_FLOAT
// RUN: %{ispc} --target=avx512skx-x16 --nowrap -O2 --emit-asm --x86-asm-syntax=intel %s -o - | FileCheck %s --check-prefixes=CHECK_ALL,CHECK_INT16,CHECK_INT32,CHECK_FLOAT
// RUN: %{ispc} --target=avx512spr-x16 --nowrap -O2 --emit-asm --x86-asm-syntax=intel %s -o - | FileCheck %s --check-prefixes=CHECK_ALL,CHECK_INT8,CHECK_INT16,CHECK_INT32,CHECK_FLOAT
// RUN: %{ispc} --target=avx512gnr-x16 --nowrap -O2 --emit-asm --x86-asm-syntax=intel %s -o - | FileCheck %s --check-prefixes=CHECK_ALL,CHECK_INT8,CHECK_INT16,CHECK_INT32,CHECK_FLOAT
// REQUIRES: X86_ENABLED && !MACOS_HOST
tests/lit-tests/3157.ispc
+6
View File
@@ -10,6 +10,12 @@
// RUN: %{ispc} --target=avx512spr-x32 --nowrap -O2 --emit-asm --x86-asm-syntax=intel %s -o - | FileCheck %s
// RUN: %{ispc} --target=avx512spr-x64 --nowrap -O2 --emit-asm --x86-asm-syntax=intel %s -o - | FileCheck %s
// RUN: %{ispc} --target=avx512gnr-x4 --nowrap -O2 --emit-asm --x86-asm-syntax=intel %s -o - | FileCheck %s
// RUN: %{ispc} --target=avx512gnr-x8 --nowrap -O2 --emit-asm --x86-asm-syntax=intel %s -o - | FileCheck %s
// RUN: %{ispc} --target=avx512gnr-x16 --nowrap -O2 --emit-asm --x86-asm-syntax=intel %s -o - | FileCheck %s
// RUN: %{ispc} --target=avx512gnr-x32 --nowrap -O2 --emit-asm --x86-asm-syntax=intel %s -o - | FileCheck %s
// RUN: %{ispc} --target=avx512gnr-x64 --nowrap -O2 --emit-asm --x86-asm-syntax=intel %s -o - | FileCheck %s
// REQUIRES: X86_ENABLED && !MACOS_HOST
// CHECK-LABEL: clz___vyi
tests/lit-tests/avx512gnr-i32x8.ispc
+43
View File
@@ -0,0 +1,43 @@
// Case 1: Checks avx512gnr-x16 assembly output for zmm registers.
//; RUN: %{ispc} %s --target=avx512gnr-x16 --emit-asm -o - 2>&1 | FileCheck %s -check-prefix=CHECK_ZMM_32x16
// Case 2a: Checks avx512gnr-x4 assembly output to ensure there are no zmm registers.
//; RUN: %{ispc} %s --target=avx512gnr-x4 --emit-asm -o - 2>&1 | FileCheck %s --implicit-check-not "zmm"
// Case 2b: Checks avx512gnr-x8 assembly output to ensure there are no zmm registers.
//; RUN: %{ispc} %s --target=avx512gnr-x8 --emit-asm -o - 2>&1 | FileCheck %s --implicit-check-not "zmm"
// Case 3: Checks avx512gnr-x16 LLVM IR to ensure avx512gnr-x8 func attributes are not present.
//; RUN: %{ispc} %s --target=avx512gnr-x16 --emit-llvm-text -o - 2>&1 | FileCheck %s --implicit-check-not ""min-legal-vector-width"="256"" --implicit-check-not ""prefer-vector-width"="256""
// Case 4a: Checks avx512gnr-x4 LLVM IR to ensure avx512gnr-x4 func attributes are present (same as for x8).
//; RUN: %{ispc} %s --target=avx512gnr-x4 --emit-llvm-text -o - 2>&1 | FileCheck %s -check-prefix=CHECK_ATTR_8
// Case 4b: Checks avx512gnr-x8 LLVM IR to ensure avx512gnr-x8 func attributes are present.
//; RUN: %{ispc} %s --target=avx512gnr-x8 --emit-llvm-text -o - 2>&1 | FileCheck %s -check-prefix=CHECK_ATTR_8
// REQUIRES: X86_ENABLED && !MACOS_HOST
double ret_round(double val)
{
//; CHECK_ZMM_32x16: zmm
return round(val+.49999);
}
double foo(double val1, double val2)
{
//; CHECK_ZMM_32x16: zmm
double sub_val = val1 - val2;
return ret_round(sub_val);
}
export void infoo(uniform double afoo1[], uniform double afoo2[], uniform double afoo3[])
{
double a = afoo1[programIndex];
double b = afoo2[programIndex];
double c = foo(a, b);
//; CHECK_ZMM_32x16: zmm
afoo3[programIndex] = c;
}
// The avx512gnr-x8 specific function attribute list will be present at 2 places.
// Once where function attributes for exported functions are aggregated and
// again where function attributes for non-exported functions are aggregated.
//; CHECK_ATTR_8: "min-legal-vector-width"="256"
//; CHECK_ATTR_8: "prefer-vector-width"="256"
//; CHECK_ATTR_8: "min-legal-vector-width"="256"
//; CHECK_ATTR_8: "prefer-vector-width"="256"
tests/lit-tests/check_dispatch.c
+3
View File
@@ -32,6 +32,9 @@ int main() {
printf("AVX512SPR\n");
break;
case 10:
printf("AVX512GNR\n");
break;
case 11:
printf("AVX10_2DMR\n");
break;
default:
tests/lit-tests/check_dispatch.ispc
+8 -4
View File
@@ -1,6 +1,6 @@
// Compile the test for different x86 targets with auto-dispatch enabled and run the test under SDE to verify that correct platform was picked in runtime.
// RUN: %{ispc} %s --target=sse2-i32x4,sse4-i32x4,avx1-i32x8,avx2-i32x8,avx2vnni-i32x8,avx512skx-x16,avx512icl-x16,avx512spr-x16 -o %t_ispc0.o --nostdlib
// RUN: %{ispc} %s --target=sse2-i32x4,sse4-i32x4,avx1-i32x8,avx2-i32x8,avx2vnni-i32x8,avx512skx-x16,avx512icl-x16,avx512spr-x16,avx512gnr-x16 -o %t_ispc0.o --nostdlib
// RUN: %{cc} -O2 %S/check_dispatch.c %t_ispc0*.o -o %t.exe
// RUN: sde -mrm -- %t.exe | FileCheck %s -check-prefix=CHECK_SSE2
// Note sse4-i32x4 implies SSE4.2 ISA, while Penryn is SSE4.1, so should fall back to SSE2.
@@ -12,15 +12,16 @@
// RUN: sde -skx -- %t.exe | FileCheck %s -check-prefix=CHECK_SKX
// RUN: sde -icl -- %t.exe | FileCheck %s -check-prefix=CHECK_ICL
// RUN: sde -spr -- %t.exe | FileCheck %s -check-prefix=CHECK_SPR
// RUN: sde -gnr -- %t.exe | FileCheck %s -check-prefix=CHECK_GNR
// RUN: %{ispc} %s --target=sse2-i32x4,sse4.1-i32x4,avx1-i32x8,avx2-i32x8,avx512skx-x16,avx512spr-x16 -o %t_ispc2.o --nostdlib
// RUN: %{ispc} %s --target=sse2-i32x4,sse4.1-i32x4,avx1-i32x8,avx2-i32x8,avx512skx-x16,avx512spr-x16,avx512gnr-x16 -o %t_ispc2.o --nostdlib
// RUN: %{cc} -O2 %S/check_dispatch.c %t_ispc2*.o -o %t2.exe
// RUN: sde -mrm -- %t2.exe | FileCheck %s -check-prefix=CHECK_SSE2
// sse4.1-i32x4 is specified, so both Penryn and Nehalem should use it.
// RUN: sde -pnr -- %t2.exe | FileCheck %s -check-prefix=CHECK_SSE4
// RUN: sde -nhm -- %t2.exe | FileCheck %s -check-prefix=CHECK_SSE4
// RUN: %{ispc} %s --target=sse2-i32x4,sse4.2-i32x4,avx1-i32x8,avx2-i32x8,avx512skx-x16,avx512spr-x16 -o %t_ispc3.o --nostdlib
// RUN: %{ispc} %s --target=sse2-i32x4,sse4.2-i32x4,avx1-i32x8,avx2-i32x8,avx512skx-x16,avx512spr-x16,avx512gnr-x16 -o %t_ispc3.o --nostdlib
// RUN: %{cc} -O2 %S/check_dispatch.c %t_ispc3*.o -o %t3.exe
// RUN: sde -mrm -- %t3.exe | FileCheck %s -check-prefix=CHECK_SSE2
// sse4.2-i32x4 is specified, so Penryn should fall back to SSE2.
@@ -37,9 +38,12 @@
// CHECK_SKX: AVX512SKX
// CHECK_ICL: AVX512ICL
// CHECK_SPR: AVX512SPR
// CHECK_GNR: AVX512GNR
export uniform int detect_isa() {
#if defined(ISPC_TARGET_AVX512SPR)
#if defined(ISPC_TARGET_AVX512GNR)
return 10;
#elif defined(ISPC_TARGET_AVX512SPR)
return 9;
#elif defined(ISPC_TARGET_AVX512ICL)
return 8;
tests/lit-tests/check_dispatch_llvm20plus.ispc
+2
View File
@@ -12,6 +12,8 @@
export uniform int detect_isa() {
#if defined(ISPC_TARGET_AVX10_2DMR)
return 11;
#elif defined(ISPC_TARGET_AVX512GNR)
return 10;
#elif defined(ISPC_TARGET_AVX512SPR)
return 9;
tests/lit-tests/disable_gather_scatter.ispc
+10
View File
@@ -55,6 +55,16 @@
// RUN: %{ispc} %s -O2 --woff --target=avx512spr-x32 --addressing=64 --nostdlib --emit-llvm-text --opt=disable-gathers --opt=disable-scatters -o - | FileCheck %s
// RUN: %{ispc} %s -O2 --woff --target=avx512spr-x64 --addressing=32 --nostdlib --emit-llvm-text --opt=disable-gathers --opt=disable-scatters -o - | FileCheck %s
// RUN: %{ispc} %s -O2 --woff --target=avx512spr-x64 --addressing=64 --nostdlib --emit-llvm-text --opt=disable-gathers --opt=disable-scatters -o - | FileCheck %s
// RUN: %{ispc} %s -O2 --woff --target=avx512gnr-x4 --addressing=32 --nostdlib --emit-llvm-text --opt=disable-gathers --opt=disable-scatters -o - | FileCheck %s
// RUN: %{ispc} %s -O2 --woff --target=avx512gnr-x4 --addressing=64 --nostdlib --emit-llvm-text --opt=disable-gathers --opt=disable-scatters -o - | FileCheck %s
// RUN: %{ispc} %s -O2 --woff --target=avx512gnr-x8 --addressing=32 --nostdlib --emit-llvm-text --opt=disable-gathers --opt=disable-scatters -o - | FileCheck %s
// RUN: %{ispc} %s -O2 --woff --target=avx512gnr-x8 --addressing=64 --nostdlib --emit-llvm-text --opt=disable-gathers --opt=disable-scatters -o - | FileCheck %s
// RUN: %{ispc} %s -O2 --woff --target=avx512gnr-x16 --addressing=32 --nostdlib --emit-llvm-text --opt=disable-gathers --opt=disable-scatters -o - | FileCheck %s
// RUN: %{ispc} %s -O2 --woff --target=avx512gnr-x16 --addressing=64 --nostdlib --emit-llvm-text --opt=disable-gathers --opt=disable-scatters -o - | FileCheck %s
// RUN: %{ispc} %s -O2 --woff --target=avx512gnr-x32 --addressing=32 --nostdlib --emit-llvm-text --opt=disable-gathers --opt=disable-scatters -o - | FileCheck %s
// RUN: %{ispc} %s -O2 --woff --target=avx512gnr-x32 --addressing=64 --nostdlib --emit-llvm-text --opt=disable-gathers --opt=disable-scatters -o - | FileCheck %s
// RUN: %{ispc} %s -O2 --woff --target=avx512gnr-x64 --addressing=32 --nostdlib --emit-llvm-text --opt=disable-gathers --opt=disable-scatters -o - | FileCheck %s
// RUN: %{ispc} %s -O2 --woff --target=avx512gnr-x64 --addressing=64 --nostdlib --emit-llvm-text --opt=disable-gathers --opt=disable-scatters -o - | FileCheck %s
// REQUIRES: X86_ENABLED && !MACOS_HOST
tests/lit-tests/dispatch.ispc
+4 -2
View File
@@ -1,6 +1,6 @@
// RUN: %{ispc} --pic --target=sse2-i32x4,sse4.1-i32x4,avx1-i32x4,avx2-i32x4,avx2vnni-i32x4,avx512icl-x4,avx512skx-x4,avx512spr-x4 -h %t.h %s -o %t.o -g
// RUN: %{ispc} --pic --target=sse2-i32x4,sse4.1-i32x4,avx1-i32x4,avx2-i32x4,avx2vnni-i32x4,avx512icl-x4,avx512skx-x4,avx512spr-x4,avx512gnr-x4 -h %t.h %s -o %t.o -g
// RUN: %{cc} -x c -c %s -o %t.c.o --include %t.h -g
// RUN: %{cc} %t.c.o -o %t.c.bin -g -rdynamic %t.o %t_sse2.o %t_sse4.o %t_avx.o %t_avx2.o %t_avx2vnni.o %t_avx512icl.o %t_avx512skx.o %t_avx512spr.o
// RUN: %{cc} %t.c.o -o %t.c.bin -g -rdynamic %t.o %t_sse2.o %t_sse4.o %t_avx.o %t_avx2.o %t_avx2vnni.o %t_avx512icl.o %t_avx512skx.o %t_avx512spr.o %t_avx512gnr.o
// RUN: sde -mrm -- %t.c.bin | FileCheck %s --check-prefix=CHECK-SSE2
// RUN: sde -pnr -- %t.c.bin | FileCheck %s --check-prefix=CHECK-SSE4
@@ -10,6 +10,7 @@
// RUN: sde -skx -- %t.c.bin | FileCheck %s --check-prefix=CHECK-SKX
// RUN: sde -icl -- %t.c.bin | FileCheck %s --check-prefix=CHECK-ICL
// RUN: sde -spr -- %t.c.bin | FileCheck %s --check-prefix=CHECK-SPR
// RUN: sde -gnr -- %t.c.bin | FileCheck %s --check-prefix=CHECK-GNR
// REQUIRES: LINUX_HOST && X86_ENABLED && SDE_INSTALLED
@@ -21,6 +22,7 @@
// CHECK-SKX: ispc_foo_avx512skx
// CHECK-ICL: ispc_foo_avx512icl
// CHECK-SPR: ispc_foo_avx512spr
// CHECK-GNR: ispc_foo_avx512gnr
#ifdef ISPC
extern "C" void print_stack_trace();
tests/lit-tests/fp16_code_gen.ispc
+5
View File
@@ -8,6 +8,11 @@
// RUN: %{ispc} %s --target=avx512spr-x32 --emit-asm -o - | FileCheck %s -check-prefix=CHECK_SPR
// RUN: %{ispc} %s --target=avx512spr-x64 --emit-asm -o - | FileCheck %s -check-prefix=CHECK_SPR
// RUN: %{ispc} %s --target=avx512gnr-x4 --emit-asm -o - | FileCheck %s -check-prefix=CHECK_SPR
// RUN: %{ispc} %s --target=avx512gnr-x8 --emit-asm -o - | FileCheck %s -check-prefix=CHECK_SPR
// RUN: %{ispc} %s --target=avx512gnr-x32 --emit-asm -o - | FileCheck %s -check-prefix=CHECK_SPR
// RUN: %{ispc} %s --target=avx512gnr-x64 --emit-asm -o - | FileCheck %s -check-prefix=CHECK_SPR
// REQUIRES: X86_ENABLED && !MACOS_HOST
// CHECK_SPR-LABEL: fp16_add
tests/lit-tests/intrinsic_target_specific.ispc
+1 -1
View File
@@ -1,7 +1,7 @@
//; RUN: %{ispc} %s --target=avx2-i32x8 --enable-llvm-intrinsics
//; RUN: %{ispc} %s --cpu=ps4 --target=avx1-i32x8 --enable-llvm-intrinsics
//; RUN: %{ispc} %s --nowrap --cpu=spr --target=avx512spr-x8 --enable-llvm-intrinsics
//; RUN: %{ispc} %s --nowrap --cpu=gnr --target=avx512spr-x8 --enable-llvm-intrinsics
//; RUN: %{ispc} %s --nowrap --target=avx512gnr-x8 --enable-llvm-intrinsics
//; RUN: not %{ispc} %s --target=sse2-i32x8 --enable-llvm-intrinsics --nowrap 2>&1 | FileCheck %s -check-prefix=CHECK_SSE2
//; REQUIRES: X86_ENABLED && !MACOS_HOST
tests/lit-tests/intrinsic_target_specific_llvm20.ispc
+1 -1
View File
@@ -1,7 +1,7 @@
//; RUN: %{ispc} %s --target=avx2-i32x8 --enable-llvm-intrinsics
//; RUN: %{ispc} %s --cpu=ps4 --target=avx1-i32x8 --enable-llvm-intrinsics
//; RUN: %{ispc} %s --nowrap --cpu=spr --target=avx512spr-x8 --enable-llvm-intrinsics
//; RUN: %{ispc} %s --nowrap --cpu=gnr --target=avx512spr-x8 --enable-llvm-intrinsics
//; RUN: %{ispc} %s --nowrap --target=avx512gnr-x8 --enable-llvm-intrinsics
//; RUN: %{ispc} %s --nowrap --cpu=dmr --target=avx10.2dmr-x8 --enable-llvm-intrinsics
//; RUN: not %{ispc} %s --target=sse2-i32x8 --enable-llvm-intrinsics --nowrap 2>&1 | FileCheck %s -check-prefix=CHECK_SSE2
tests/lit-tests/intrinsics_amx_fp16.ispc
+2 -2
View File
@@ -1,8 +1,8 @@
// This test checks that AMX FP16 (amxfp16) intrinsics are correctly handled by ISPC
// RUN: not %{ispc} --nowrap %s --target=avx512spr-x4 --enable-llvm-intrinsics --emit-llvm-text -O2 -o - 2>&1 | FileCheck %s -check-prefix=CHECK_SPR_ERROR
// RUN: %{ispc} --nowrap %s --target=avx512spr-x4 --cpu=gnr --enable-llvm-intrinsics --emit-llvm-text -O2 -o - 2>&1 | FileCheck %s -check-prefix=CHECK_GNR_SUCCESS
// RUN: %{ispc} --nowrap %s --target=avx10.2dmr-x4 --cpu=dmr --enable-llvm-intrinsics --emit-llvm-text -O2 -o - 2>&1 | FileCheck %s -check-prefix=CHECK_DMR_SUCCESS
// RUN: %{ispc} --nowrap %s --target=avx512gnr-x4 --enable-llvm-intrinsics --emit-llvm-text -O2 -o - 2>&1 | FileCheck %s -check-prefix=CHECK_GNR_SUCCESS
// RUN: %{ispc} --nowrap %s --target=avx10.2dmr-x4 --enable-llvm-intrinsics --emit-llvm-text -O2 -o - 2>&1 | FileCheck %s -check-prefix=CHECK_DMR_SUCCESS
// REQUIRES: X86_ENABLED && LLVM_20_0+ && !MACOS_HOST
tests/lit-tests/intrinsics_amx_int8.ispc
+2 -2
View File
@@ -2,8 +2,8 @@
// RUN: not %{ispc} --nowrap %s --target=avx512icl-x4 --enable-llvm-intrinsics --emit-llvm-text -O2 -o - 2>&1 | FileCheck %s -check-prefix=CHECK_ICL_ERROR
// RUN: %{ispc} --nowrap %s --target=avx512spr-x4 --enable-llvm-intrinsics --emit-llvm-text -O2 -o - 2>&1 | FileCheck %s -check-prefix=CHECK_SPR_SUCCESS
// RUN: %{ispc} --nowrap %s --target=avx512spr-x4 --cpu=gnr --enable-llvm-intrinsics --emit-llvm-text -O2 -o - 2>&1 | FileCheck %s -check-prefix=CHECK_GNR_SUCCESS
// RUN: %{ispc} --nowrap %s --target=avx10.2dmr-x4 --cpu=dmr --enable-llvm-intrinsics --emit-llvm-text -O2 -o - 2>&1 | FileCheck %s -check-prefix=CHECK_DMR_SUCCESS
// RUN: %{ispc} --nowrap %s --target=avx512gnr-x4 --enable-llvm-intrinsics --emit-llvm-text -O2 -o - 2>&1 | FileCheck %s -check-prefix=CHECK_GNR_SUCCESS
// RUN: %{ispc} --nowrap %s --target=avx10.2dmr-x4 --enable-llvm-intrinsics --emit-llvm-text -O2 -o - 2>&1 | FileCheck %s -check-prefix=CHECK_DMR_SUCCESS
// REQUIRES: X86_ENABLED && LLVM_20_0+ && !MACOS_HOST
tests/lit-tests/intrinsics_amx_tile.ispc
+2 -2
View File
@@ -2,8 +2,8 @@
// RUN: not %{ispc} --nowrap %s --target=avx512icl-x4 --enable-llvm-intrinsics --emit-llvm-text -O2 -o - 2>&1 | FileCheck %s -check-prefix=CHECK_ICL_ERROR
// RUN: %{ispc} --nowrap %s --target=avx512spr-x4 --enable-llvm-intrinsics --emit-llvm-text -O2 -o - 2>&1 | FileCheck %s -check-prefix=CHECK_SPR_SUCCESS
// RUN: %{ispc} --nowrap %s --target=avx512spr-x4 --cpu=gnr --enable-llvm-intrinsics --emit-llvm-text -O2 -o - 2>&1 | FileCheck %s -check-prefix=CHECK_GNR_SUCCESS
// RUN: %{ispc} --nowrap %s --target=avx10.2dmr-x4 --cpu=dmr --enable-llvm-intrinsics --emit-llvm-text -O2 -o - 2>&1 | FileCheck %s -check-prefix=CHECK_DMR_SUCCESS
// RUN: %{ispc} --nowrap %s --target=avx512gnr-x4 --enable-llvm-intrinsics --emit-llvm-text -O2 -o - 2>&1 | FileCheck %s -check-prefix=CHECK_GNR_SUCCESS
// RUN: %{ispc} --nowrap %s --target=avx10.2dmr-x4 --enable-llvm-intrinsics --emit-llvm-text -O2 -o - 2>&1 | FileCheck %s -check-prefix=CHECK_DMR_SUCCESS
// REQUIRES: X86_ENABLED && LLVM_20_0+ && !MACOS_HOST
tests/lit-tests/perf-warnings.ispc
+6 -1
View File
@@ -32,8 +32,13 @@
// RUN: %{ispc} %s --nostdlib --nowrap --target=avx512spr-x16 -o %t.o 2>&1 | FileCheck %s -check-prefix=CHECK_AVX512
// RUN: %{ispc} %s --nostdlib --nowrap --target=avx512spr-x32 -o %t.o 2>&1 | FileCheck %s -check-prefix=CHECK_AVX512
// RUN: %{ispc} %s --nostdlib --nowrap --target=avx512spr-x64 -o %t.o 2>&1 | FileCheck %s -check-prefix=CHECK_AVX512
// RUN: %{ispc} %s --nostdlib --nowrap --target=avx512gnr-x4 -o %t.o 2>&1 | FileCheck %s -check-prefix=CHECK_AVX512
// RUN: %{ispc} %s --nostdlib --nowrap --target=avx512gnr-x8 -o %t.o 2>&1 | FileCheck %s -check-prefix=CHECK_AVX512
// RUN: %{ispc} %s --nostdlib --nowrap --target=avx512gnr-x16 -o %t.o 2>&1 | FileCheck %s -check-prefix=CHECK_AVX512
// RUN: %{ispc} %s --nostdlib --nowrap --target=avx512gnr-x32 -o %t.o 2>&1 | FileCheck %s -check-prefix=CHECK_AVX512
// RUN: %{ispc} %s --nostdlib --nowrap --target=avx512gnr-x64 -o %t.o 2>&1 | FileCheck %s -check-prefix=CHECK_AVX512
// A note about notrunning on macOS - it's because of SPR not being supported there.
// A note about not running on macOS - it's because of SPR/GNR not being supported there.
// It should be sufficient to run this test on other platforms and not to complicate
// with splitting it to SPR and non-SPR versions.
// REQUIRES: X86_ENABLED && !MACOS_HOST
tests/lit-tests/target_x86_macos_no_spr.ispc
+14 -7
View File
@@ -1,14 +1,21 @@
// The test checks that target definitions for SPR are not accepted on macOS.
// The test checks that target definitions for SPR and GNR are not accepted on macOS.
//; RUN: not %{ispc} %s -o %t.o --nostdlib --target-os=macos --arch=x86-64 --nowrap --target=avx512spr-x4 2>&1 | FileCheck %s
//; RUN: not %{ispc} %s -o %t.o --nostdlib --target-os=macos --arch=x86-64 --nowrap --target=avx512spr-x8 2>&1 | FileCheck %s
//; RUN: not %{ispc} %s -o %t.o --nostdlib --target-os=macos --arch=x86-64 --nowrap --target=avx512spr-x16 2>&1 | FileCheck %s
//; RUN: not %{ispc} %s -o %t.o --nostdlib --target-os=macos --arch=x86-64 --nowrap --target=avx512spr-x32 2>&1 | FileCheck %s
//; RUN: not %{ispc} %s -o %t.o --nostdlib --target-os=macos --arch=x86-64 --nowrap --target=avx512spr-x64 2>&1 | FileCheck %s
//; RUN: not %{ispc} %s -o %t.o --nostdlib --target-os=macos --arch=x86-64 --nowrap --target=avx512spr-x4 2>&1 | FileCheck %s -check-prefix=CHECK_SPR
//; RUN: not %{ispc} %s -o %t.o --nostdlib --target-os=macos --arch=x86-64 --nowrap --target=avx512spr-x8 2>&1 | FileCheck %s -check-prefix=CHECK_SPR
//; RUN: not %{ispc} %s -o %t.o --nostdlib --target-os=macos --arch=x86-64 --nowrap --target=avx512spr-x16 2>&1 | FileCheck %s -check-prefix=CHECK_SPR
//; RUN: not %{ispc} %s -o %t.o --nostdlib --target-os=macos --arch=x86-64 --nowrap --target=avx512spr-x32 2>&1 | FileCheck %s -check-prefix=CHECK_SPR
//; RUN: not %{ispc} %s -o %t.o --nostdlib --target-os=macos --arch=x86-64 --nowrap --target=avx512spr-x64 2>&1 | FileCheck %s -check-prefix=CHECK_SPR
//; RUN: not %{ispc} %s -o %t.o --nostdlib --target-os=macos --arch=x86-64 --nowrap --target=avx512gnr-x4 2>&1 | FileCheck %s -check-prefix=CHECK_GNR
//; RUN: not %{ispc} %s -o %t.o --nostdlib --target-os=macos --arch=x86-64 --nowrap --target=avx512gnr-x8 2>&1 | FileCheck %s -check-prefix=CHECK_GNR
//; RUN: not %{ispc} %s -o %t.o --nostdlib --target-os=macos --arch=x86-64 --nowrap --target=avx512gnr-x16 2>&1 | FileCheck %s -check-prefix=CHECK_GNR
//; RUN: not %{ispc} %s -o %t.o --nostdlib --target-os=macos --arch=x86-64 --nowrap --target=avx512gnr-x32 2>&1 | FileCheck %s -check-prefix=CHECK_GNR
//; RUN: not %{ispc} %s -o %t.o --nostdlib --target-os=macos --arch=x86-64 --nowrap --target=avx512gnr-x64 2>&1 | FileCheck %s -check-prefix=CHECK_GNR
// REQUIRES: X86_ENABLED && MACOS_HOST
// CHECK: Error: avx512spr-x{{.*}} target for x86-64 on macOS is not supported in current build.
// CHECK_SPR: Error: avx512spr-x{{.*}} target for x86-64 on macOS is not supported in current build.
// CHECK_GNR: Error: avx512gnr-x{{.*}} target for x86-64 on macOS is not supported in current build.
uniform int j;
tests/lit-tests/targets_x86_llvm14plus.ispc
+6
View File
@@ -6,6 +6,12 @@
//; RUN: %{ispc} %s -o %t.o --nostdlib --target=avx512spr-x32
//; RUN: %{ispc} %s -o %t.o --nostdlib --target=avx512spr-x64
//; RUN: %{ispc} %s -o %t.o --nostdlib --target=avx512gnr-x4
//; RUN: %{ispc} %s -o %t.o --nostdlib --target=avx512gnr-x8
//; RUN: %{ispc} %s -o %t.o --nostdlib --target=avx512gnr-x16
//; RUN: %{ispc} %s -o %t.o --nostdlib --target=avx512gnr-x32
//; RUN: %{ispc} %s -o %t.o --nostdlib --target=avx512gnr-x64
// REQUIRES: X86_ENABLED && !MACOS_HOST
uniform int j;
tests/lit-tests/vnni-1.ispc
+3
View File
@@ -5,13 +5,16 @@
// RUN: %{ispc} %s --target=avx512icl-x4 --emit-asm -o - | FileCheck %s -check-prefixes=CHECK_ALL,CHECK_XMM
// RUN: %{ispc} %s --target=avx512spr-x4 --emit-asm -o - | FileCheck %s -check-prefixes=CHECK_ALL,CHECK_XMM
// RUN: %{ispc} %s --target=avx512gnr-x4 --emit-asm -o - | FileCheck %s -check-prefixes=CHECK_ALL,CHECK_XMM
// RUN: %{ispc} %s --target=avx512icl-x8 --emit-asm -o - | FileCheck %s -check-prefixes=CHECK_ALL,CHECK_YMM
// RUN: %{ispc} %s --target=avx512spr-x8 --emit-asm -o - | FileCheck %s -check-prefixes=CHECK_ALL,CHECK_YMM
// RUN: %{ispc} %s --target=avx512gnr-x8 --emit-asm -o - | FileCheck %s -check-prefixes=CHECK_ALL,CHECK_YMM
// RUN: %{ispc} %s --target=avx512icl-x16 --emit-asm -o - | FileCheck %s -check-prefixes=CHECK_ALL,CHECK_ZMM
// RUN: %{ispc} %s --target=avx512icl-x16 --opt=disable-zmm --emit-asm -o - | FileCheck %s -check-prefixes=CHECK_ALL,CHECK_YMM
// RUN: %{ispc} %s --target=avx512spr-x16 --emit-asm -o - | FileCheck %s -check-prefixes=CHECK_ALL,CHECK_ZMM
// RUN: %{ispc} %s --target=avx512gnr-x16 --emit-asm -o - | FileCheck %s -check-prefixes=CHECK_ALL,CHECK_ZMM
// REQUIRES: X86_ENABLED && !MACOS_HOST
tests/lit-tests/vnni-2.ispc
+2
View File
@@ -2,9 +2,11 @@
// RUN: %{ispc} %s --target=avx512icl-x32 --emit-asm -o - | FileCheck %s -check-prefixes=CHECK_ALL,CHECK_ZMMX2
// RUN: %{ispc} %s --target=avx512spr-x32 --emit-asm -o - | FileCheck %s -check-prefixes=CHECK_ALL,CHECK_ZMMX2
// RUN: %{ispc} %s --target=avx512gnr-x32 --emit-asm -o - | FileCheck %s -check-prefixes=CHECK_ALL,CHECK_ZMMX2
// RUN: %{ispc} %s --target=avx512icl-x64 --emit-asm -o - | FileCheck %s -check-prefixes=CHECK_ALL,CHECK_ZMMX4
// RUN: %{ispc} %s --target=avx512spr-x64 --emit-asm -o - | FileCheck %s -check-prefixes=CHECK_ALL,CHECK_ZMMX4
// RUN: %{ispc} %s --target=avx512gnr-x64 --emit-asm -o - | FileCheck %s -check-prefixes=CHECK_ALL,CHECK_ZMMX4
// REQUIRES: X86_ENABLED && !MACOS_HOST
tools/check_isa.cpp
+6 -9
View File
@@ -47,13 +47,12 @@ const char *const isa_strings[] = {
"SKX",
"ICL",
"SPR",
"GNR",
"DMR",
};
static const char *spr_amx_on = "SPR (AMX on)";
static const char *spr_amx_off = "SPR (AMX off)";
static const char *lGetSystemISA() {
static char amx_isa_string[32];
#if defined(__arm__) || defined(__aarch64__) || defined(_M_ARM64)
return "ARM NEON";
#elif defined(__i386__) || defined(__x86_64__) || defined(_M_IX86) || defined(_M_X64)
@@ -62,12 +61,10 @@ static const char *lGetSystemISA() {
return "Unknown x86 ISA";
}
const char *isa = isa_strings[isa_id];
if (isa_id == SPR_AVX512) {
if (__os_enabled_amx_support()) {
return spr_amx_on;
} else {
return spr_amx_off;
}
if (isa_id >= SPR_AVX512) {
snprintf(amx_isa_string, sizeof(amx_isa_string), "%s (AMX %s)", isa,
__os_enabled_amx_support() ? "on" : "off");
return amx_isa_string;
}
return isa;
#elif defined(__riscv)