* Adding a method to clear the processor cache. Signed-off-by: Cédrik Fuoco <cedrik.fuoco@autodesk.com> * Do not clear the cache when enabling the cache Adding test for the cache enable/disable cycle Adding test to test clearProcessorCache Signed-off-by: Cédrik Fuoco <cedrik.fuoco@autodesk.com> * Unrelated: Changing zlib version to 1.2.8 (adding it to this PR to minimize PRs) Signed-off-by: Cédrik Fuoco <cedrik.fuoco@autodesk.com> * Documentations Tweak unit tests FIx implementation for clearProcessorCache Signed-off-by: Cédrik Fuoco <cedrik.fuoco@autodesk.com> * Documentations reverting zlib version and will do it in another PR Signed-off-by: Cédrik Fuoco <cedrik.fuoco@autodesk.com> * Documentation and python binding Signed-off-by: Cédrik Fuoco <cedrik.fuoco@autodesk.com> * Adding python unit tests and minor fixes Signed-off-by: Cédrik Fuoco <cedrik.fuoco@autodesk.com> * Missing change from last commit Signed-off-by: Cédrik Fuoco <cedrik.fuoco@autodesk.com> --------- Signed-off-by: Cédrik Fuoco <cedrik.fuoco@autodesk.com> Co-authored-by: Doug Walker <doug.walker@autodesk.com>
72 lines
2.1 KiB
Python
72 lines
2.1 KiB
Python
# SPDX-License-Identifier: BSD-3-Clause
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# Copyright Contributors to the OpenColorIO Project.
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import unittest, os, sys
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import PyOpenColorIO as OCIO
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from UnitTestUtils import (TEST_DATAFILES_DIR)
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class ProcessorCacheTest(unittest.TestCase):
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def test_processor_cache(self):
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CONFIG = """ocio_profile_version: 2
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search_path: """ + TEST_DATAFILES_DIR + """
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strictparsing: true
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luma: [0.2126, 0.7152, 0.0722]
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environment: {CS3: lut1d_green.ctf}
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roles:
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default: cs1
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displays:
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disp1:
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- !<View> {name: view1, colorspace: cs3}
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colorspaces:
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- !<ColorSpace>
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name: cs1
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- !<ColorSpace>
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name: cs2
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from_scene_reference: !<MatrixTransform> {offset: [0.11, 0.12, 0.13, 0]}
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- !<ColorSpace>
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name: cs3
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from_scene_reference: !<FileTransform> {src: $CS3}
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"""
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cfg = OCIO.Config.CreateFromStream(CONFIG)
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cfg.validate()
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# Test that clearProcessorCache clears the Processor cache.
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# Create two processors and confirm that it is the same object as expected
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procA = cfg.getProcessor("cs3", "disp1", "view1", OCIO.TRANSFORM_DIR_FORWARD)
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procB = cfg.getProcessor("cs3", "disp1", "view1", OCIO.TRANSFORM_DIR_FORWARD)
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# Comparing the address of both Processor objects to confirm if they are the same or not.
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self.assertEqual(procA, procB)
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cfg.clearProcessorCache()
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# Create a third processor and confirm that it is different from the previous two as the
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# the processor cache was cleared.
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procC = cfg.getProcessor("cs3", "disp1", "view1", OCIO.TRANSFORM_DIR_FORWARD)
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self.assertNotEqual(procC, procA)
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# Test that disable and re-enable the cache, using setProcessorCacheFlags, does not
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# clear the Processor cache.
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procD = cfg.getProcessor("cs3", "disp1", "view1", OCIO.TRANSFORM_DIR_FORWARD)
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# Disable and re-enable the processor cache.
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cfg.setProcessorCacheFlags(OCIO.PROCESSOR_CACHE_OFF)
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cfg.setProcessorCacheFlags(OCIO.PROCESSOR_CACHE_ENABLED)
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# Confirm that the processor is the same.
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procE = cfg.getProcessor("cs3", "disp1", "view1", OCIO.TRANSFORM_DIR_FORWARD)
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self.assertEqual(procD, procE) |